參數(shù)資料
型號: 84221
廠商: LSI Corporation
英文描述: Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device (Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications)(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器))
中文描述: 四100BaseTX/100BaseFX/10BaseT物理層裝置(高度集成的以太網(wǎng)收發(fā)器,雙絞線和光纖以太網(wǎng)的應用)(四通道100BaseTX/100BaseFX/10BaseT物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器) )
文件頁數(shù): 5/70頁
文件大?。?/td> 1017K
代理商: 84221
MD400184/A
5
84221
1.0 PIN DESCRIPTION (cont’d)
Controller Interface (RMII)
Pin #
Pin Name
I/O
Description
127
CLKIN
I
Clock Input.
This controller interface input latches controller interface data in and out of
the device on rising edges for all channels. There must be a 50 Mhz clock
tied to this pin.
104
91
75
61
TXEN_[3:0]
I
Transmit Enable Input.
high to allow data on TXD and TXER to be clocked in on the rising edges of
CLKIN.
These interface inputs must be be asserted active
[106:105]
[93:92]
[77:76]
[63:62]
TXD[1:0]_3
TXD[1:0]_2
TXD[1:0]_1
TXD[1:0]_0
I
Transmit Data Input.
transmitted on the TP outputs and are clocked in on rising edges of CLKIN.
These interface inputs contain input di-bit data to be
107
97
82
68
CRS_DV[3:0]
O
Carrier Sense Output.
when valid data is detected on the receive TP inputs and is clocked out on
the rising edge of CLKIN.
These interface outputs are asserted active high
[100:101]
[85:86]
[69:70]
[57:58]
RXD[1:0]_3
RXD[1:0]_2
RXD[1:0]_1
RXD[1:0]_0
O
Receive Data Output.
from the TP inputs and are clocked out on the rising edges of CLKIN.
These interface outputs contain recovered di-bit data
103
88
72
59
RXER_[3:0]
O
Receive Error Output.
when coding or other specified errors are detected on the TP inputs and are
clocked out on rising edges of CLKIN.
These interface outputs are asserted active high
相關PDF資料
PDF描述
84301 84301 4-Port Fast Ethernet Controller manual 3/98
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