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參數(shù)資料
| 型號： | 84221 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 15/70頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | 84221 |
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MD400184/A
15
84221
RMII receive outputs. This predetermined threshold level
can be configured to be either 4 bits or 16 bits by appropri-
ately setting the receive buffer threshold select bit in the
MI serial port Global Configuration register. If the elastic
buffer underflows or overflows, RXER is asserted and
RXD[1:0]=01 for all data bits from the underflow/overflow
detect point until the end of the packet.
RXER is a receive error output that is asserted when cer-
tain errors are detected on the receive data. RXER is
asserted on rising edge of CLKIN for all data bits of the
packet starting from the RXER detect point until the end of
the packet. In addition, any packet that contains an
RXER will substitute RXD[1:0]=01 for all the data bits from
the RXER detect point until the end of packet.
There is no collision indication for RMII. Collision can be
sensed external to the device when both TXEN and CRS
are asserted at the same time. Also, there is no internal
TXEN loopback in RMII mode.
2.2.3 10 Mbps
10 Mbps RMII operation is identical to 100 Mbps RMII
operation, except: (1) Each transmit data di-bit must be
input on TXD[1:0] for ten consecutive CLKIN cycles, and
(2) Each receive data di-bit will be output on RXD[1:0] for
ten consecutive CLKIN cycles.
2.2.4 RMII Disable
The RMII inputs and outputs can be disabled by setting
the MII disable bit in the MI serial port Control register.
When the RMII is disabled, the inputs are ignored, the out-
puts are placed in high impedance state, and the TP out-
put is high impedance.
2.3 ENCODER
2.3.1 4B5B Encoder - 100 Mbps
100BaseTX requires that this data be 4B5B encoded.
4B5B coding converts the 4 bit data nibbles into 5 bit
data words. The mapping of the 4B nibbles to the 5B code
words is specified in IEEE 802.3 and shown in Table 2.
The 4B5B encoder on the 84221 takes 4B nibbles from
the controller interface, converts them into 5B words
according to, Table 2, and sends the 5B words to the
scrambler. The 4B5B encoder also substitutes the first
eight bits of the preamble with the SSD delimiters (/J/K/
symbols) and adds an ESD delimiter (/T/R/ symbols) to
the end of each packet, as defined in IEEE 802.3 and
shown in Figure 2. The 4B5B encoder also fills the
period between packets, called the idle period, with a
continuous stream of idle symbols, as shown in Figure 2.
Table 2. 4B/5B Symbol Mapping
* These 5B codes are not used. For decoder, these 5B codes
are decoded to 4B 0000. For encoder, 4B 0000 is encoded
to 5B 11110, as shown in symbol 0.
2.3.2 Manchester Encoder - 10 Mbps
The Manchester encoding process combines clock and
NRZ data such that the first half of the data bit contains
the complement of the data, and the second half of the
data bit contains the true data, as specified in IEEE 802.3.
This guarantees that a transition always occurs in the
middle of the bit cell. The 84221 Manchester encoder
converts the 10 Mbps NRZ data from the controller
interface into a single data stream for the TP transmitter
and adds a start of idle pulse (SOI) at the end of the
packet as specified in IEEE 802.3 and shown in Figure 2.
Symbol
Name
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Description
5B Code
4B Code
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
I
Idle
11111
0000
J
K
T
R
H
SSD #1
SSD #2
ESD #1
ESD #2
Halt
11000
10001
01101
00111
00100
0101
0101
0000
0000
Undefined
---
Invalid codes
All others*
0000*
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