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參數(shù)資料
| 型號(hào)： | 83C196EA |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS 16-Bit Microcontroller(CHMOS型 16位微控制器) |
| 中文描述： | CHMOS 16位微控制器（CHMOS型16位微控制器） |
| 文件頁(yè)數(shù)： | 29/46頁(yè) |
| 文件大小： | 376K |
| 代理商： | 83C196EA |
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ADVANCE INFORMATION
23
83C196EA
— AUTOMOTIVE
6.3
AC Characteristics — Demultiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 9. AC Characteristics, Demultiplexed Bus Mode (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
F
XTAL1
Frequency on XTAL1, PLL in 1x mode
20
40
MHz (
1
,
8
)
Frequency on XTAL1, PLL in 2x mode
10
20
MHz (
8
)
f
Operating frequency, f = F
XTAL1
; PLL in 1x mode
20
40
Mhz
Operating frequency, f = 2F
XTAL1
; PLL in 2x mode
t
Period, t = 1/f
25
50
ns
T
AVDV
T
RLDV
T
AVWL
T
AVRL
T
SLDV
T
CHDV
T
RHDZ
T
RHRL
T
RXDX
T
XHCH
T
CLCL
Address Valid to Input Data Valid
4t – 23
ns (
2
)
RD# Low to Input Data Valid
3t – 25
ns (
2
)
Address Valid to WR# Low
t
ns
Address Valid to RD# Low
t – 8
ns
Chip Select Low to Data Valid
4t – 27
ns (
2
)
CLKOUT Rising Edge to Input Data Valid
2t – 25
ns (
9
)
RD# High to Input Data Float
t - 5
ns
Read High to Next Read Low
t – 5
ns
Data Hold after RD# Inactive
0
ns
XTAL1 High to CLKOUT High or Low
10
35
ns (
9
)
CLKOUT Cycle Time
2t
ns (
9
)
T
CHCL
T
CLLH
T
RLCL
T
RLRH
T
RHLH
T
WLCL
T
QVWH
NOTES:
1.
CLKOUT High Period
t – 10
t + 10
ns (
9
)
CLKOUT Falling ALE Rising
– 10
10
ns (
9
)
RD# Low to CLKOUT Low
– 5
5
ns (
9
)
RD# Low to RD# High
3t – 12
ns (
2
)
RD# Rising to ALE Rising
t – 4
t + 12
ns (
3
)
WR# Low to CLKOUT Falling
– 13
5
ns (
9
)
Data Stable to WR# Rising Edge
3t – 18
ns (
3
)
20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz
can be applied with an external clock source.
If wait states are used, add 2t
×
n
, where
n
= number of wait states.
Assuming back-to-back bus cycles.
When forcing wait states using the BUSCON register, add 2t
×
n.
Exceeding the maximum specification causes additional wait states.
8-bit bus only.
The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
wait state is required.
Device is static by design but has been tested only down to 20 MHz.
Assumes CLKOUT is operating in divide-by-two mode (f/2).
2.
3.
4.
5.
6.
7.
8.
9.
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|---|---|
| 83C196KB16 | BOX W/LID ABS BLACK 4.3X3.2X1.6,1 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 83C196KB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER |
| 83C196KB16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER |
| 83C196KD | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:COMMERCIAL CHMOS MICROCONTROLLER |
| 83C196KD20 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:COMMERCIAL CHMOS MICROCONTROLLER |
| 83C196LC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS 16-BIT MICROCONTROLLER |
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