參數(shù)資料
型號(hào): 83C196EA
廠商: Intel Corp.
英文描述: CHMOS 16-Bit Microcontroller(CHMOS型 16位微控制器)
中文描述: CHMOS 16位微控制器(CHMOS型16位微控制器)
文件頁(yè)數(shù): 25/46頁(yè)
文件大?。?/td> 376K
代理商: 83C196EA
ADVANCE INFORMATION
19
83C196EA
— AUTOMOTIVE
6.2
AC Characteristics — Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
F
XTAL1
Frequency on XTAL1, PLL in 1x mode
20
40
MHz (
1
,
8
)
Frequency on XTAL1, PLL in 2x mode
10
20
MHz (
8
)
f
Operating frequency, f = F
XTAL1
; PLL in 1x mode
20
40
MHz (
8
)
Operating frequency, f = 2F
XTAL1
; PLL in 2x mode
t
Period, t = 1/f
25
50
ns
T
AVDV
T
RLDV
T
CHDV
T
RHDZ
T
RXDX
T
XHCH
T
CLCL
T
CHCL
T
CLLH
T
LLCH
T
LHLH
T
LHLL
T
AVLL
T
LLAX
T
LLRL
T
RLCL
T
RLRH
T
RHLH
NOTES:
1.
Address Valid to Input Data Valid
3t – 40
ns (
2
)
RD# Low to Input Data Valid
t – 23
ns (
2
)
CLKOUT High to Input Data valid
2t – 35
ns (
9
)
RD# High to Input Data Float
t + 5
ns
Data Hold after RD# Inactive
0
ns
XTAL1 Rising Edge to CLKOUT High or Low
3
50
ns (
9
)
CLKOUT Cycle Time
2t
ns (
9
)
CLKOUT High Period
t – 10
t + 10
ns (
9
)
CLKOUT Falling to ALE Rising
– 10
10
ns (
9
)
ALE Falling to CLKOUT Rising
– 10
10
ns (
9
)
ALE Cycle Time
4t
ns (
2
)
ALE High Period
t – 10
t + 10
ns
Address Setup to ALE Low
t – 15
ns
Address Hold after ALE Low
t – 16
ns
ALE Low to RD# Low
t – 15
ns
RD# Low to CLKOUT Low
– 10
10
ns (
9
)
RD# Low to RD# High
t – 12
ns (
2
)
RD# High to ALE Rising
t – 5
t + 15
ns (
3
)
20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz
can be applied with an external clock source.
If wait states are used, add 2t
×
n
, where
n
= number of wait states.
Assuming back-to-back bus cycles.
When forcing wait states using the BUSCON register, add 2t
×
n.
Exceeding the maximum specification causes additional wait states.
8-bit bus only.
The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed
wait state is required.
Device is static by design but has been tested only down to 20 MHz.
Assumes CLKOUT is operating in divide-by-two mode (f/2).
2.
3.
4.
5.
6.
7.
8.
9.
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