參數(shù)資料
型號(hào)： 83C196EA
廠商： Intel Corp.
英文描述： CHMOS 16-Bit Microcontroller(CHMOS型 16位微控制器)
中文描述： CHMOS 16位微控制器（CHMOS型16位微控制器）
文件頁(yè)數(shù)： 13/46頁(yè)
文件大小： 376K
代理商： 83C196EA
ADVANCE INFORMATION
7
83C196EA
— AUTOMOTIVE
4.0
SIGNALS
Table 4. Signal Descriptions (Sheet 1 of 8)
Name
Type
O
Description
A15:0
System Address Bus
These address lines provide address bits 0–15 during the entire external mem-
ory cycle during both multiplexed and demultiplexed bus modes.
Address Lines 16–20
These address lines provide address bits 16–20 during the entire external
memory cycle, supporting extended addressing of the 2 Mbyte address space.
NOTE:
Internally, there are 24 address bits; however, only 21 external
address pins (A20:0) are implemented. The internal address space is
16 Mbytes (000000 FFFFFFH) and the external address space is
2 Mbytes (00000 1FFFFFH). The device resets to FF2080H in internal
memory or 1F2080H in external memory.
A20:16 are multiplexed with EPORT.4:0.
Analog Channels
These pins are analog inputs to the A/D converter.
The ANGND and V
REF
pins must be connected for the A/D converter to function.
Address/Data Lines
The function of these pins depend on the bus size and mode. When a bus
access is not occurring, these pins revert to their I/O port function.
16-bit Multiplexed Bus Mode
:
AD15:0 drive address bits 0–15 during the first half of the bus cycle and drive or
receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode
:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive
address bits 0–7 during the first half of the bus cycle and drive or receive data
during the second half of the bus cycle.
16-bit Demultiplexed Mode
:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode
:
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data
that is currently on the high byte of the internal bus.
AD7:0 share package pins P3.7:0. AD15:8 share package pins P4.7:0.
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus (A20:16 and AD15:0
for a multiplexed bus; A20:0 for a demultiplexed bus).
An external latch can use this signal to demultiplex address bits 0–15 from the
address/data bus in multiplexed mode.
ALE shares a package pin with P5.0.
Analog Ground
ANGND must be connected for A/D converter operation. ANGND and V
SS
should be nominally at the same potential.
A20:16
I/O
ACH15:0
I
AD15:0
I/O
ALE
O
ANGND
GND
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