參數(shù)資料
型號(hào)： 82801E
廠商： INTEL CORP
元件分類： 外設(shè)及接口
英文描述： Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述： MULTIFUNCTION PERIPHERAL, PBGA421
封裝： BGA-421
文件頁數(shù)： 65/84頁
文件大小： 1196K
代理商： 82801E
Intel
82801E C-ICH
Advance Information Datasheet
65
t74
PIORDY/SIORDY Inactive Pulse Width
48
ns
15
t75
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width
Low
2,3
15, 16
t76
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width
High
3,4
15, 16
Table 46. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)
Sym
Parameter (1)
Mode 0 (ns)
Mode 1 (ns)
Mode 2 (ns)
Figure
Min
Max
Min
Max
Min
Max
t80
Sustained Cycle Time (T2cyctyp)
240
160
120
t81
Cycle Time (Tcyc)
112
73
54
18
t82
Two Cycle Time (T2cyc)
230
154
115
18
t83
Data Setup Time (Tds)
15
10
7
18
t84
Data Hold Time (Tdh)
5
5
5
18
t85
Data Valid Setup Time (Tdvs)
70
48
30
18
t86
Data Valid Hold Time (Tdvh)
6
6
6
18
t87
Limited Interlock Time (Tli)
0
150
0
150
0
150
20
t88
Interlock Time w/ Minimum (Tmli)
20
20
20
20
t89
Envelope Time (Tenv)
20
70
20
70
20
70
17
t90
Ready to Pause Time (Trp)
160
125
100
19
t91
DMACK setup/hold Time (Tack)
20
20
20
17,
20
NOTE:
1. The specification symbols in parentheses correspond to the Ultra ATA specification name.
Table 45. IDE PIO & Multiword DMA Mode Timing (Sheet 2 of 2)
Sym
Parameter
Min
Max
Units
Notes
Figure
NOTES:
1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock.
2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI
clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register
3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width
cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE
timing register.
4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or
greater. Refer to the RCT field in the IDE Timing Register.
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