參數(shù)資料
型號(hào)： 82596DX
廠商： Intel Corp.
英文描述： HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
中文描述： 高性能的32位局域網(wǎng)協(xié)處理器
文件頁(yè)數(shù)： 69/77頁(yè)
文件大?。?/td> 787K
代理商： 82596DX
82596DX/SX
SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS
The measurements should be done at:
#
T
C
e
0
§
C–85
§
C, V
CC
e
5V
g
10%, C
e
50 pF unless otherwise specified.
#
A.C. testing inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V for a logic ‘‘0’’.
#
Timing measurements are made at 1.5V for both logic ‘‘1’’ and ‘‘0’’.
#
Rise and Fall time of inputs and outputs signals are measured between 0.8V and 2.0V respectively unless
otherwise specified.
#
All timings are relative to CLK2 crossing the 1.5V level.
#
All A.C. parameters are valid only after 100
m
s from power up.
290219–18
290219–19
Figure 46. CLK2 Timings
Two types of timing specifications are presented below:
1. Input TimingDminimum setup and hold times.
2. Output TimingsDoutput delays and float times from CLK2 rising edge.
Figure 45 defines how the measurements should be done:
290219–20
LEGEND:
Ts
e
Input Setup Time
Th
e
Input Hold Time
Tn
e
Minimum output delay or Mininum float delay
Tx
e
Maximum output delay or Maximum float delay
Figure 47. Drive Levels and Measurements Points for A.C. Specifications
69
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82596SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
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