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參數(shù)資料
| 型號： | 82596DX |
| 廠商： | Intel Corp. |
| 英文描述： | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 中文描述： | 高性能的32位局域網協(xié)處理器 |
| 文件頁數(shù)： | 45/77頁 |
| 文件大?。?/td> | 787K |
| 代理商： | 82596DX |
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82596DX/SX
where:
EL, B, C, I, S
D As per standard Command Block (see the NOP command for details).
OK (Bit 13)
D Error free completion.
A (Bit 12)
D Indicates that the command was abnormally terminated due to CU Abort control
command. If 1, then the command was aborted, and if necessary it should be
repeated. If this bit is 0, the command was not aborted.
Bits 19–28
D Reserved (0 in the 32-bit Segmented and Linear modes).
CMD (Bits 16–18)
D The transmit command: 4h.
Status Bit 11
D Late collision. A late collision (a collision after the slot time is elapsed) is detected.
Status Bit 10
D No Carrier Sense signal during transmission. Carrier Sense signal is monitored
from the end of Preamble transmission until the end of the Frame Check Sequence
for TONOCRS
e
1 (Transmit On No Carrier Sense mode) it indicates that transmis-
sion has been executed despite a lack of CRS. For TONOCRS
e
0 (Ethernet
mode), this bit also indicates unsuccessful transmission (transmission stopped
when lack of Carrier Sense has been detected).
Status Bit 9
D Transmission unsuccessful (stopped) due to Loss of CTS.
Status Bit 8
D Transmission unsuccessful (stopped) due to DMA Underrun; i.e., the system did
not supply data for transmission.
Status Bit 7
D Transmission Deferred, i.e., transmission was not immediate due to previous link
activity.
Status Bit 6
D Heartbeat Indicator, Indicates that after a previously performed transmission, and
before the most recently performed transmission, (Interframe Spacing) the CDT
signal was monitored as active. This indicates that the Ethernet Transceiver Colli-
sion Detect logic is performing properly. The Heartbeat is monitored during the
Interframe Spacing period.
Status Bit 5
D Transmission attempt was stopped because the number of collisions exceeded the
maximum allowable number of retries.
Status Bit 4
D 0 (Reserved).
D The number of Collisions experienced during this frame. Max Col
e
0 plus S5
e
1
indicates 16 collisions.
MAX-COL
(Bits 3–0)
LINK OFFSET
D As per standard Command Block (see the NOP for details).
TBD POINTER
D In the 82586 and 32-bit Segmented modes this is the offset of the first Tx Buffer
Descriptor containing the data to be transmitted. In the Linear mode this is the 32-
bit address of the first Tx Buffer Descriptor on the list. If the TBD POINTER is all 1s
it indicates that no TBD is used.
DEST ADDRESS
D Contains the Destination Address of the frame. The least significant bit (MC) indi-
cates the address type.
MC
e
0: Individual Address.
MC
e
1: Multicast or Broadcast Address.
If the Destination Address bits are all 1s this is a Broadcast Address.
LENGTH FIELD
D The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is transmitted; i.e., most
significant byte first, least significant byte second.
TCB COUNT
D This 14-bit counter indicates the number of bytes that will be transmitted from the
Transmit Command Block, starting from the third byte after the TCB COUNT field
(address n
a
12 in the 32-bit Segmented mode, N
a
16 in the Linear mode). The
TCB COUNT field can be any number of bytes (including an odd byte), this allows
the user to transmit a frame with a header having an odd number of bytes. The
TCB COUNT field is not used in the 82586 mode.
EOF Bit
D Indicates that the whole frame is kept in the Transmit Command Block. In the
Simplified memory model it must be always asserted.
45
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相關代理商/技術參數(shù) |
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|---|---|
| 82596SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
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| 82-5988-1000 | 功能描述:RF 連接器 N RIGHT ANGLE CRIMP PLUG RoHS:否 制造商:Bomar Interconnect 產品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型: |
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