參數(shù)資料
型號(hào)： 82596DX
廠商： Intel Corp.
英文描述： HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
中文描述： 高性能的32位局域網(wǎng)協(xié)處理器
文件頁(yè)數(shù)： 3/77頁(yè)
文件大?。?/td> 787K
代理商： 82596DX
82596DX/SX
INTRODUCTION
The 82596DX/SX is an intelligent, high-performance
32-bit
Local
Area
Network
82596DX/SX implements the CSMA/CD access
method and can be configured to support all exist-
ing
IEEE
802.3
standardsDTYPEs
10BASE5, 10BASE2, 1BASE5, and 10BROAD36. It
can also be used to implement the proposed stan-
dard TYPE 10BASE-F. The 82596DX/SX performs
high-level commands, command chaining, and inter-
processor communications via shared memory, thus
relieving the host CPU of many tasks associated
with network control. All time-critical functions are
performed independently of the CPU, this increases
network
performance
82596DX/SX bus interface is optimized for Intel’s
i386
TM
DX and i386
TM
SX microprocessors.
coprocessor.
The
10BASE-T,
and
efficiency.
The
The 82596DX/SX implements all IEEE 802.3 Medi-
um Access Control and channel interface functions,
these include framing, preamble generation and
stripping, source address generation, destination ad-
dress checking, short-frame detection, and automat-
ic length-field handling. Data rates up to 20 Mb/s are
supported.
The 82596DX/SX provides a powerful host system
interface. It manages memory structures automati-
cally, with command chaining and bidirectional data
chaining. An on-chip DMA controller manages four
channels, this allows autonomous transfer of data
blocks (buffers and frames) and relieves the CPU of
byte transfer overhead. Buffers containing errored or
collided frames can be automatically recovered with-
out CPU intervention. The 82596DX/SX provides an
upgrade path for existing 82586 software drivers by
providing an 82586-software-compatible mode that
supports the current 82586 memory structure. The
82596DX/SX also has a Flexible memory structure
and a Simplified memory structure. The 82596DX/
SX can address up to 4 gigabytes of memory. The
82596DX/SX supports Little Endian and Big Endian
byte ordering.
The 82596DX/SX bus interface is optimized to In-
tel’s i386
TM
DX and i386 SX microprocessors, pro-
viding a bus transfer rate of up to 66 MB/s at
33 MHz. The bus interface employs bus throttle tim-
ers to regulate 82596DX/SX bus use. Two large, in-
dependent FIFOsD128 bytes for Receive and 64
bytes for TransmitDtolerate long bus latencies and
provide programmable thresholds that allow the
user to optimize bus overhead for any worst-case
bus latency.
The 82596DX/SX provides a wide range of diagnos-
tics and network management functions, these in-
clude internal and external loopback, exception con-
dition tallies, channel activity indicators, optional
capture of all frames regardless of destination ad-
dress (promiscuous mode), optional capture of er-
rored or collided frames, and time domain reflectom-
etry for locating fault points on the network cable.
The statistical counters, in 32-bit segmented and lin-
ear modes, are 32-bits each and include CRC errors,
alignment errors, overrun errors, resource errors,
short
frames,
and
received
82596DX/SX also features a monitor mode for net-
work analysis. In this mode the 82596DX/SX can
capture status bytes, and update statistical coun-
ters, of frames monitored on the link without trans-
ferring the contents of the frames to memory. This
can be done concurrently while transmitting and re-
ceiving frames destined for that station.
collisions.
The
The 82596DX/SX can be used in both baseband
and broadband networks. It can be configured for
maximum network efficiency (minimum contention
overhead) with networks of any length. Its highly
flexible CSMA/CD unit supports address field
lengths of zero through six bytes for IEEE 802.3/
Ethernet frame delimitation. It also supports 16- or
32-bit cyclic redundancy checks. The CRC can be
transferred directly to memory for receive, opera-
tions or dynamically inserted for transmit operations.
The CSMA/CD unit can also be configured for full
duplex operation for high throughput in point-to-point
connections.
The 82596 C-Step incorporates several new fea-
tures not found in previous steppings. The following
is a summary of the 82596 C-step’s new features.
#
The 82596 C-step fixes Errata found in the A1
and B steppings.
#
The 82596 C-step has improved AC timings over
both the A and B steppings.
#
The 82596 C-step has a New Enhanced Big Endi-
an Mode where in Linear Addressing mode, true
32-bit Big Endian functionality is achieved. New
Enhanced Big Endian Mode is enabled by setting
bit 7 of the SYSBUS byte. This mode is software
compatible with the big endian mode of the B-
step with one exceptionDno 32-bit addresses
need to be swapped by software in the C-step. In
this new mode, the 82596 C-step treats 32-bit ad-
dress pointers as true 32-bit entities and the SCB
absolute address and statistical counters are still
treated as two 16-bit big endian entities. Not set-
ting this mode will configure the 82596 C-step to
be 100% compatible to the A1-step bit endian
mode.
#
The 82596 C-step is hardware and software com-
patible to both the A1 and B steppings allowing
for easy ‘‘drop-in’’ to current designs. Pinout and
control structures remain unchanged.
The 82596DX/SX is fabricated with Intel’s reliable,
5-V, CHMOS IV (Process 648.8) technology. It is
available in a 132-pin PQFP or PGA package.
3
相關(guān)PDF資料
PDF描述
82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
8261SHAKE22 Alternate Action and Momentary Pushbutton Switches
8261SHAKE223 Alternate Action and Momentary Pushbutton Switches
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