參數(shù)資料
型號(hào)： 82596DX
廠商： Intel Corp.
英文描述： HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
中文描述： 高性能的32位局域網(wǎng)協(xié)處理器
文件頁數(shù)： 67/77頁
文件大?。?/td> 787K
代理商： 82596DX
82596DX/SX
TRANSMIT/RECEIVE CLOCK PARAMETERS
(Continued)
Symbol
Parameter
20 MHz
Notes
Min
Max
RECEIVED DATA PARAMETERS
(Continued)
T60
RxD Rise Time
10
T61
RxD Fall Time
10
CRS AND CDT PARAMETERS
T62
CDT Low to TxC HIGH
External Collision Detect Setup Time
20
T63
TxC High to CDT Inactive, CDT Hold Time
10
T64
CDT Low to Jam Start
10
T65
CRS Low to TxC High,
Carrier Sense Setup Time
20
T66
TxC High to CRS Inactive, CRS Hold Time
10
T67
CRS High to Jamming Start,
(Internal Collision Detect)
12
T68
Jamming Period
11
T69
CRS High to RxC High,
CRS Inactive Setup Time
30
T70
RxC High to CRS High,
CRS Inactive Hold Time
10
INTERFRAME SPACING PARAMETERS
T71
Interframe Delay
9
EXTERNAL LOOPBACK-PIN PARAMETERS
T72
TxC Low to LPBK Low
T36
4
T73
TxC Low to LPBK High
T36
4
NOTES:
1. Special MOS levels, V
CIL
e
0.9V and V
CIH
e
3.0V.
2. Manchester only.
3. Manchester. Needs 50% duty cycle.
4. 1 TTL load
a
50 pF.
5. 1 TTL load
a
100 pF.
6. NRZ only.
7. Abnormal end of transmissionDCTS expires before RTS.
8. Normal end to transmission.
9. Programmable value:
T71
e
N
IFS
T36
where: N
IFS
e
the IFS configuration value
(if N
IFS
is less than 12 then N
IFS
is forced to 12).
10. Programmable value:
T64
e
(N
T36)
a
x
#
T36
(If the collision occurs after the preamble)
where:
N
e
the collision detect filter configuration value, and
x
e
12, 13, 14, or 15
11. T68
e
32
#
T36
12. Programmable value:
T67
e
(N
CSF
T36)
a
x
#
T36
where: N
CSF
e
the Carrier Sense Filter configuration value, and
x
e
12, 13, 14, or 15
13. To guarantee recognition on the next clock.
67
相關(guān)PDF資料
PDF描述
82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
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參數(shù)描述
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