參數(shù)資料
型號(hào)： 82546EB
廠商： Intel Corp.
英文描述： Dual Port Gigabit Ethernet Controller
中文描述： 雙端口千兆以太網(wǎng)控制器
文件頁(yè)數(shù)： 14/47頁(yè)
文件大?。?/td> 281K
代理商： 82546EB
82546EB
— Networking Silicon
8
Datasheet
3.0
Signal Descriptions
Note:
The targeted signal names are subject to change without notice. Verify with your local Intel sales
office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the
82546EB
controller are electrically defined as follows:
3.2
PCI Bus Interface
When the Reset signal (RST#) is asserted, the
82546EB
will not drive any PCI output or bi-
directional pins except the Power Management Event signal (PME#).
3.2.1
PCI Address, Data and Control Signals
Name
Definition
I
Input.
Standard input only digital signal.
O
Output.
Standard output only digital signal.
TS
Tri-state.
Bi-directional three-state digital input/output signal.
STS
Sustained Tri-state.
Sustained digital three-state signal driven by one agent at a time.
An agent driving the STS pin low must actively drive it high for at least one clock before letting it
float. The next agent of the signal cannot drive the pin earlier than one clock after it has been
released by the previous agent.
OD
Open Drain.
Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a
weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore
the signal to the de-asserted state.
A
Analog.
PHY analog data signal.
P
Power.
Power connection, voltage reference, or other reference connection.
R
Reserved.
Symbol
Type
Name and Function
AD[63:0]
TS
Address and Data.
Address and data signals are multiplexed on the same PCI pins. A
bus transaction includes an address phase followed by one or more data phases.
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted
low. During the address phase
AD[63:0]
contain a physical address
(64 bits)
. For I/O,
this is a byte address, and for configuration and memory, a DWORD address. The
82546EB
device uses little endian byte ordering.
During data phases, AD[7:0] contain the least significant byte (LSB) and
AD[63:56]
contain the most significant byte (MSB).
The 82546EBcontroller may optionally be connected to a 32-bit PCI bus. On the 32-bit
bus, AD[63:32] and other signals corresponding to the high order byte lanes do not
participate in the bus cycle.
相關(guān)PDF資料
PDF描述
8254 PROGRAMMABLE INTERVAL TIMER
82555 10/100 Mbps LAN physical layer interface
82557 Fast Ethernet PCI Bus Controller(快速以太網(wǎng) PCI總線控制器)
82559 Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器)
8255A-5 PROGRAMMABLE PERIPHEAL INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82546GB 制造商:INT 功能描述: 制造商:undefined 功能描述:
825470 功能描述:UC-EMLP (27X12 5) YE 制造商:phoenix contact 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:10
82547-00000 制造商:3M Electronic Products Division 功能描述:ADAM ref. traded PUR
825479-2 制造商:TE Connectivity 功能描述:MOD II VERT.MNT MAL - Bulk
825479-3 制造商:TE Connectivity 功能描述:MOD II VERT.MNT MAL - Bulk
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