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Datasheet
Revision History
Date
Revision
Notes
Aug 2003
2.0
Non-classified release.
Mar 2004
3.0
Updated Section 4, “Voltage, Temperature, and Timing Specifications,” for the
C-0 stepping.
Oct 2004
3.1
Corrected EEMODE signal description.
Updated signal names to match design guide and reference schematics.
Nov 2004
3.2
Added lead free information.
Added information about migrating from a 2-layer 0.36 mm wide-trace
substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section
on Package and Pinout Information.
Added statement that no changes to existing soldering processes are
needed for the 2-layer 0.32 mm wide-trace substrate change in the
section describing “Package Information”.
Corrected pinout discrepancies between sections “Signal Descriptions”
and “Package and Pinout Information”.
Jan 2005
3.3
Added new maximum values for DC supply voltages on 1.2 V and 1.8 V
pins. See Table 2, Recommended Operating Conditions and Table 6, DC
Characteristics.
Feb 2005
3.4
Updated Visual Pin Assignment diagram for pinouts F9, F10, E14, F14,
and H14.
Apr 2005
3.5
Removed all references to CLK_RUN# signal.
Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash
functionality is not used then an external pull-down resistor is required.
July 2005
3.6
Added pin C8 description to Table 29 and Table 31.
Aug 2005
3.7
Corrected 25 MHz Clock Input Requirements in Table 13.
June 2006
3.8
Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash
functionality is not used then an external pull-up resistor is required.
June 2006
3.9
Updated Table 13 “25 MHz Clock Input Requirements”.
Aug 2006
4.0
Updated Table 40 descriptions for pins A10, B10, and C9.
Updated pinout descriptions from Tables 25 - 42 to match Figure 13.
Sept 2006
4.1
Removed note “b” from Table 2 and note “a” from Tables 3 and 4. Moved
the note following Table 5 before Table 3 “3.3V Supply Voltage Ramp”
.
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