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Advance Information
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Data Sheet
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80960RM
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
80960RM Functional Block Diagram............................................................... 8
80960JT Core Block Diagram ....................................................................... 11
540L H-PBGA Package Diagram (Top and Side View) ................................ 25
540L H-PBGA Package Diagram (Bottom View) .......................................... 26
Thermocouple Attachment - A) No Heatsink / B) With Heatsink................... 37
VCC5REF Current-Limiting Resistor............................................................. 42
V
CCPLL
Lowpass Filter .................................................................................. 42
P_CLK, TCLK, DCLKIN, DCLKOUT Waveform............................................ 50
T
OV
Output Delay Waveform......................................................................... 50
T
OF
Output Float Waveform.......................................................................... 51
T
IS
and T
IH
Input Setup and Hold Waveform................................................ 51
I
2
C Interface Signal Timings.......................................................................... 51
AC Test Load (all signals except SDRAM and Flash signals)....................... 52
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Related Documentation................................................................................... 7
Instruction Set .............................................................................................. 14
Pin Description Nomenclature....................................................................... 16
Memory Controller Signals............................................................................ 17
Primary PCI Bus Signals............................................................................... 20
Secondary PCI Arbiter Signals...................................................................... 21
Secondary PCI Bus Signals.......................................................................... 22
JX Core Signals and Configuration Straps.................................................... 23
I
2
C, JTAG, Core Signals ............................................................................... 24
540-Lead H-PBGA Package
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Signal Name Order..................................... 27
540-Lead H-PBGA Pinout
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Ballpad Number Order.................................... 32
540-Lead H-PBGA Package Thermal Characteristics .................................. 38
Heat Sink Vendors and Contacts .................................................................. 39
Socket-Header Vendor.................................................................................. 40
Burn-in Socket Vendor .................................................................................. 40
Shipping Tray Vendor.................................................................................... 40
Logic Analyzer Interposer Vendor................................................................. 40
JTAG Emulator Vendor................................................................................. 40
Operating Conditions..................................................................................... 41
V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V)......... 42
DC Characteristics ........................................................................................ 43
I
CC
Characteristics ........................................................................................ 44
Input Clock Timings....................................................................................... 44
SDRAM Output Clock Timings...................................................................... 45
PCI Signal Timings....................................................................................... 46
JN Core Signal Timings................................................................................. 47
SDRAM / Flash Signal Timings..................................................................... 47
Boundary Scan Test Signal Timings ............................................................. 48
I2C Interface Signal Timings ......................................................................... 49
Device ID Registers....................................................................................... 53