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參數(shù)資料
| 型號(hào)： | 80960SA |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded 32-Bit Microprocessor With 16-Bit Burst Data Bus(帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式 32-BIT微處理器) |
| 中文描述： | 嵌入式32位微處理器，16位突發(fā)數(shù)據(jù)總線（帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式32位微處理器） |
| 文件頁數(shù)： | 1/39頁 |
| 文件大?。?/td> | 374K |
| 代理商： | 80960SA |
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Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
INTEL CORPORATION, 1993
November 1993
Order Number: 272206-002
80960SA
EMBEDDED 32-BIT MICROPROCESSOR
WITH 16-BIT BURST DATA BUS
The 80960SA is a member of Intel’s i960
32-bit processor family, which is designed especially for low cost
embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960SA
has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC
technology, this high performance processor is capable of execution rates in excess of 7.5 million instructions
per second
. The 80960SA is well-suited for a wide range of cost sensitive embedded applications including
non-impact printers, network adapters and I/O controllers.
Figure 1. The 80960SA Processor’s Highly Parallel Architecture
*
Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11 is a trademark of Digital Equipment
Corporation)
I
High-Performance Embedded
Architecture
— 20 MIPS* Burst Execution at 20 MHz
— 7.5 MIPS Sustained Execution
at 20 MHz
I
512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
I
Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
I
Pin Compatible with 80960SB
I
Built-in Interrupt Controller
— 4 Direct Interrupt Pins
— 31 Priority Levels, 256 Vectors
I
Easy to Use, High Bandwidth 16-Bit Bus
— 32 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
I
32-Bit Address Space, 4 Gigabytes
I
80-Lead Quad Flat Pack (EIAJ QFP)
— 84-Lead Plastic Leaded Chip Carrier
(PLCC)
I
Software Compatible with
80960KA/KB/CA/CF Processors
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
INSTRUCTION
EXECUTION
UNIT
64- BY 32-BIT
LOCAL
REGISTER
CACHE
SIXTEEN
32-BIT GLOBAL
REGISTERS
32-BIT
ADDRESS
16-BIT
BURST
BUS
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