參數(shù)資料
型號(hào)： 80960RM
廠(chǎng)商： Intel Corp.
英文描述： 80960RM I/O Processor(80960RM I/O 處理器)
中文描述： 80960RM I / O處理器（80960RM的I / O處理器）
文件頁(yè)數(shù)： 47/54頁(yè)
文件大?。?/td> 855K
代理商： 80960RM
Data Sheet
—
80960RM
Advance Information
47
4.5.3
JN Core Interface Timings
4.5.4
SDRAM/Flash Interface Signal Timings
Table 26.
JN Core Signal Timings
Symbol
Parameter
Min
Max
Units
Notes
T
OV5
Output Valid Delay from
P_CLK
-
FAIL#
2
TBD
ns
(1,5)
T
IS7
Input Setup to
P_CLK
-
NMI#
,
XINT[5:4]#
25
ns
(2,3)
T
IH5
Input Hold from
P_CLK
-
NMI#
,
XINT[5:4]#
2
ns
(2,3)
NOTES:
1. See
Figure 9
“
TOV Output Delay Waveform
”
on page 50
.
2. See
Figure 11
“
TIS and TIH Input Setup and Hold Waveform
”
on page 51
.
3. Setup and hold times must be met for proper processor operation.
NMI#
and
XINT[5:4]#
may be
synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock
edge. For asynchronous operation,
NMI#
and
XINT[5:4]#
must be asserted for a minimum of two
P_CLK
periods to guarantee recognition.
4. Core signals include:
XINT[5:4]#
,
NMI#
,
FAIL#
.
5. The processor asserts
FAIL#
during built-in self-test. If self-test passes,
FAIL#
is deasserted. The
processor asserts
FAIL#
during the bus confidence test. If the test passes,
FAIL#
is deasserted and user
program execution begins.
Table 27.
SDRAM / Flash Signal Timings
Symbol
Parameter
Min
Max
Units
Notes
T
OV6
Output Valid Delay from
DCLKIN
-
SA[11:0]
,
SBA[1:0]
,
SCAS#
,
SRAS#
, and
SWE#
.
1.62
6.6
ns
(1,5)
T
OV7
Output Valid Delay from
DCLKIN
-
DQ[63:0]
, and
SCB[7:0]
.
2.03
7.14
ns
(1,5)
T
OV8
Output Valid Delay from
DCLKIN
-
SDQM[7:0]
2.57
6.85
ns
(1,5)
T
OV9
Output Valid Delay from
DCLKIN
-
SCKE[1:0]
1.74
5.5
ns
(1,5)
T
OV10
Output Valid Delay from
DCLKIN
-
SCE[1:0]#
1.65
5.25
ns
(1,5)
T
IS8
Input Setup to
DCLKIN
-
DQ[63:0]
, and
SCB[7:0]
3
ns
(2)
T
IH6
Input Hold from
DCLKIN
-
DQ[63:0]
, and
SCB[7:0]
1.5
ns
(2)
T
OV11
Output Valid Delay from
DCLKIN
- RAD[16:0]
,
RALE
,
RCE[1:0]#
,
ROE#
, and
RWE#
.
1.4
11
ns
(1,5)
T
IS9
Input Setup to
DCLKIN
- RAD[16:0]
5
ns
(2)
T
IH7
Input Hold from
DCLKIN
- RAD[16:0]
1.4
ns
(2)
NOTES:
1. See
Figure 9
“
TOV Output Delay Waveform
”
on page 50
.
2. See
Figure 11
“
TIS and TIH Input Setup and Hold Waveform
”
on page 51
.
3. SDRAM signals include
SA[11:0]
,
SBA[1:0]
,
SCAS#
,
SCE[1:0]#
,
SCKE[1:0]
,
SDQM[7:0]
,
SRAS#
,
SWE#
,
DQ[63:0]
, and
SCB[7:0]
. Timings are for 3.3V signalling environment.
4. Flash signals include RAD[16:0],
RALE
,
RCE[1:0]#
,
ROE#
, and
RWE#
. Timings are for 5 V signalling
environment.
5. These output valid times are specified with a 0 pF loading.
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