![](http://datasheet.mmic.net.cn/230000/7751_datasheet_15568130/7751_81.png)
7751 Group User’s Manual
INT E R R UPT S
4–26
4.11 Precautions when using interrupts
4.11 Precautions when using interrupts
To change the interrupt priority level select bits (bits 0 to 2 at addresses 70
16
to 7F
16
), 2 to 7 cycles of
φ
are required after executing an write-instruction until completion of the interrupt priority level’s change.
Accordingly, it is necessary to reserve enough time by software when changing the interrupt priority level
of which interrupt source is the same within a very short execution time consisting of a few instructions.
Figure 4.11.1 shows a program example to reserve time required for changing interrupt priority level. The
time for change depends on the interrupt priority detection timer select bits (bits 4 and 5 at address 5E
16
).
Table 4.11.1 lists the relation between the number of instructions to be inserted with program example of
Figure 4.11.1 and the interrupt priority detection time select bits.
Fig. 4.11.1 Program example to reserve time required for changing interrupt priority level
Table 4.11.1 Relation between number of instructions to be inserted with program example of Figure
4.11.1 and interrupt priority detection time select bits
Interrupt priority detection time select bits
(Note)
Interrupt priority level
b5
0
0
1
1
1
Note:
We recommend [b5 = “1”, b4 = “0”].
detection time
7 cycles of
φ
4 cycles of
φ
2 cycles of
φ
Do not select.
Number of inserted
instructions
NOP
instruction 4 or more
NOP
instruction 2 or more
NOP
instruction 1 or more
b4
0
1
0
; Write to interrupt priority level select bits
; Insert
NOP
instruction
(Note)
;
;
; Write to interrupt priority level select bits
Note:
All instructions (other than instructions for writing to address 7X
16
) which have the
same cycles as
NOP
instruction can also be inserted. Confirm the number of
instructions to be inserted by Table 4.11.1.
:
LDM.B #0XH, 007XH
NOP
NOP
NOP
LDM.B #0XH, 007XH
: