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T IME R A
7751 Group User’s Manual
5–25
5.4 Event counter mode
(1) Switching between up-count and down-count
The up-down register (address 44
16
) or the input signal from the TAi
OUT
pin is used to switch the up-
count from and to the down-count. This switching is performed by the up-down bit when the up-down
switching factor select bit (bit 4 at addresses 56
16
to 5A
16
) is “0,” and by the input signal from the
TAi
OUT
pin when the up-down switching factor select bit is “1.”
When switching the up-count/down-count, this switching is actually performed when the count source’s
next valid edge is input.
G
Switching by up-down bit
The counter down-counts when the up-down bit is “0,” and up-counts when the up-down bit is “1.”
Figure 5.4.5 shows the structure of the up-down register.
G
Switching by TAi
OUT
pin’s input signal
The counter down-counts when the TAi
OUT
pin’s input signal is at “L” level, and up-counts when the
TAi
OUT
pin’s input signal is at “H” level.
When using the TAi
OUT
pin input signal to switch the up-count/down-count, set the port P5 and P6
direction registers’ bits which correspond to the TAi
OUT
pin for the input mode.
Fig. 5.4.5 Structure of up-down register
Bit
Bit name
At reset
0
0
0
0
0
RW
Functions
b7
b6
b5
b4
b3
b2
b1
b0
Up-down register (Address 44
16
)
0
0
0
Timer A4 up-down bit
Timer A3 up-down bit
Timer A2 up-down bit
Timer A1 up-down bit
Timer A0 up-down bit
Timer A2 two-phase pulse signal
processing select bit
(Note)
Timer A3 two-phase pulse signal
processing select bit
(Note)
Timer A4 two-phase pulse signal
processing select bit
(Note)
0 : Down-count
1 : Up-count
This function is valid when the
contents of the up-down register are
selected as the up-down switching
factor.
0 : Disabled Two-phase pulse signal
processing function
1 : Enabled Two-phase pulse signal
processing function
When not using the two-phase pulse
signal processing function, make
sure to set the bit to “0.”
The value is “0” at reading.
Note:
Use the
LDM
or
STA
instruction when writing to bits 5 to 7.
0
1
2
3
4
5
6
7
RW
RW
RW
RW
RW
WO
WO
WO