CE NT R AL PR OCE SSING UNIT (CPU)
2.1 Central processing unit
2–6
7751 Group User’s Manual
2.1.7 Data bank register (DT)
The data bank register is an 8-bit register. In the following addressing modes using the data bank register,
the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed.
Use the
LDT
instruction to set a value to this register.
In the single-chip mode, make sure to fix this register to “00
16
”. It is because the access space of the
single-chip mode is the internal area within the bank 0
16
.
This register is cleared to “00
16
” at reset.
G
Addressing modes using data bank register
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Absolute
Absolute bit
Absolute indexed X
Absolute indexed Y
Absolute bit relative
Stack pointer relative indirect indexed Y
Multiplied accumulation
2.1.8 Direct page register (DPR)
The direct page register is a 16-bit register. The contents of this register indicate the direct page area
which is allocated in bank 0
16
or in the space across banks 0
16
and 1
16
. The following addressing modes
use the direct page register.
The contents of the direct page register indicate the base address (the lowest address) of the direct page
area. The space which extends to 256 bytes above that address is specified as a direct page.
The direct page register can contain a value from “0000
16
” to “FFFF
16
.” When it contains a value equal to
or more than “FF01
16
,” the direct page area spans the space across banks 0
16
and 1
16
.
When the contents of low-order 8 bits of the direct page register is “00
16
,” the number of cycles required
to generate an address is 1 cycle smaller than the number when its contents are not “00
16
.” Accordingly,
the access efficiency can be enhanced in this case.
This register is cleared to “0000
16
” at reset.
Figure 2.1.4 shows a setting example of the direct page area.
G
Addressing modes using direct page register
Direct
Direct bit
Direct indexed X
Direct indexed Y
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Direct bit relative