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CONNE CT ION WIT H E X T E R NAL DE VICE S
7751 Group User’s Manual
12–19
12.4 Hold function
12.4.1 Operation description
Judgment timing of the input level of the HOLD pin depends on the state using the bus. While the bus is
not in use, the judgment is performed at every falling of
φ
BIU
. While the bus is in use, the judgment timing
depends on the bus cycle. Table 12.4.2 lists the judgment timing of the input level of the HOLD pin during
the used bus.
Additionally, when accessing word data beginning from an odd address with 2-bus cycle, the judgment is
performed only at the second bus cycle. (See Figure 12.4.1.)
When “L” level is detected at judgment of the input level, the microcomputer enters Hold state. (This is
called acceptance of Hold request.)
_____
When the Hold request is accepted,
φ
CPU
stops next rising of
φ
BIU
. At the same time, the HLDA pin’s level
φ
BIU
has passed after the level of HLDA pin becomes “L”, pins R/W,
___
BHE, and the external bus become floating state.
In Hold state, the input level of the HOLD pin is judged at every falling of
φ
BIU
. Then, when “H” level is
detected, the HLDA pin’s level changes “L” to “H” next rising of
φ
BIU
. When 1 cycle of
φ
BIU
has passed after
the level of HLDA pin becomes “H”, the microcomputer terminates Hold state.
Figures 12.4.2 to 12.4.4 show timing of acceptance of Hold request and termination of Hold state.
Note:
φ
BIU
has a same polarity and a same frequency as the clock
φ
1
. However,
φ
BIU
stops by acceptance
of the Ready request, or executing the
STP
or
WIT
instruction. Accordingly, judgment of the input
level of the HOLD pin is not performed during Ready state.
Clock
1
BIU
ALE
Reading
Writing
Judgment timing of input level to HOLD pin
No judge
Judge
Accessing word data with 2-bus cycle.
(Example of 2
access in low-speed running
)
E
A
A
A
W
A
W
Fig. 12.4.1 Judgment when accessing word data beginning from odd address with 2-bus cycle