
MITSUBISHI MICROCOMPUTERS
7630 Group
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Baud rate selection
The baud rate of transmission and reception is determined by the
setting of the prescaler and the contents of the UART baud rate
generator register. It is calculated by: where pis the division ratio of
the prescaler and nis the content of UART baud rate generator reg-
ister. The prescalers division ration can be selected by the UART
mode register (see below).
UART mode register (UMOD, Structure of UART
mode register)
The UART mode register allows to select the transmission and
reception format with the following options:
word length: 7, 8 or 9 bits
parity: none, odd or even
stop bits: 1 or 2
It allows to select the prescalers division ratio as well.
UART baud rate generator (UBRG)
This 8 bit register allows to select the baud rate of the UART (see
above). Set this register to the desired value before enabling recep-
tion or transmission.
UART control register (UCON, Structure of UART
control register)
The UART control register consists of four control bits (bit 0 to bit 3)
which allow to control reception and transmission.
UART status register (USTS, Structure of UART
status register)
The read-only UART status register consists of 7 bits (bit 0 to bit 6)
which indicate the operating status of the UART function and vari-
ous errors.
(3) Handshaking signals
When used as transmitter the UART will recognize the clear-to-
send signal via P2
7
/UCTS terminal for handshaking. When used as
receiver it will issue a request-to-send signal through P2
6
/URTS
pin.
Clear-to-send input
When used as a transmitter (transmit enable bit set to “1”), the
UART starts transmission after recognizing “L” level on P2
7
/UCTS.
After started the UART will continue to transmit regardless of the
actual level of P2
7
/UCTS or status of the transmit enable bit.
Request-to-send output
The UART controls the P2
6
/URTS output according to the following
conditions.
Table 5: Output control conditions
Fig. 26
Block diagram of UART
b
16
p
n
1
+
(
)
----------------------------------
=
Condition
P2
6
/URTS
Receive enable bit is set to “1”
Reception completed during receive enable
bit set to “1”
Start bit (falling edge) detected
Receive enable bit is set to “0” before recep-
tion started
Hardware reset
Receive initialization bit is set to “1”
“L”
“H”
UMOD
4,3,2
transmission
control circuit
φ
1
1/8
1/32
1/256
UMOD
2, 1
UBRG (8)
transmit shift register (9)
reception control
circuit
P2
5
/UTXD
P2
7
/UCTS
P2
6
/URTS
bit counter
bit counter
UMOD
7, 6
UMOD
7, 6
UART status register
transmit buffer empty flag
receive error flags
receive buffer full interrupt request
receive buffer full flag
receive error interrupt request
P2
4
/URXD
transmit buffer (9)
data bus
data bus
transmit buffer empty interrupt request
transmit register empty interrupt request
transmit register empty flag
receive shift register (9)
receive buffer (9)
UART control register
“00”
“01”
“10”
“11”