參數(shù)資料
型號(hào): 7630
英文描述: 7630 Group Datasheet Datasheet 840K/JAN.13.99
中文描述: 7630組數(shù)據(jù)表數(shù)據(jù)表840K/JAN.13.99
文件頁(yè)數(shù): 41/49頁(yè)
文件大?。?/td> 840K
代理商: 7630
40
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 7630 group is equipped with an internal clock generating cir-
cuit.
Please refer to Fig. 46 for a circuit example using a ceramic resona-
tor or quartz crystal oscillator. For the capacitor values, refer to the
manufacturers recommended parameters which depend on each
oscillators characteristics. When using an external clock, input it to
the X
IN
pin and leave X
OUT
open.
Fig. 46
Ceramic resonator circuit
.
Oscillation Control
The 7630 group has two low power modes: the stop and the wait
mode.
Stop mode
The microcomputer enters the stop mode by executing the STP
instruction. The oscillator stops with the internal clock
φ
at “H” level.
Timers 1 and 2 will be cascaded and initialized by their reload
latches contents. The count source for timer 1 will be set to
f(X
IN
)/16.
Oscillation is restarted if an external interrupt is accepted or at
reset. When using an external interrupt, the internal clock
φ
remains
at “H” level until timer 2 underflows allowing a time-out until the
clock oscillation becomes stable. When using reset, a fixed time-out
will be generated allowing oscillation to stabilize.
Wait mode
The microcomputer enters the wait mode by executing the WIT
instruction. The internal clock stops at “H” level while the oscillator
keeps running.
Recovery from wait mode can be done in the same way as from
stop mode. However, the time-out period mentioned above is not
required to return from wait-mode, thus no such time-out mecha-
nism has been implemented.
Note: Set the interrupt enable bit of the interrupt source to be used
to return from stop or wait mode to “1” before executing STP or WIT
instruction.
Fig. 47
Block diagram of clock generating circuit
C
IN
C
OUT
X
IN
X
OUT
WIT
STP
X
IN
X
OUT
1/2
1/4
CPUM
6
interrupt request
interrupt disable flag
RESET
S
R
Q
delay
STP
D
T
Q
D
T
Q
R
S
Q
R
S
Q
R
S
Q
STP
P2
internal clock
for
peripherals
internal clock
for CPU
oscillator countdown
(timer 1 and 2)
2
φ
φ
“1”
“0”
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