參數(shù)資料
型號: 7630
英文描述: 7630 Group Datasheet Datasheet 840K/JAN.13.99
中文描述: 7630組數(shù)據(jù)表數(shù)據(jù)表840K/JAN.13.99
文件頁數(shù): 24/49頁
文件大?。?/td> 840K
代理商: 7630
MITSUBISHI MICROCOMPUTERS
7630 Group
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMER 1, TIMER 2, TIMER 3
Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one com-
mon pre-divider. Timer 1 can operate in the timer mode only,
whereas timers 2 and 3 can be used to generate a PWM output sig-
nal timing as well. Timers 1 to 3 are down count timers. See Fig. 21.
Fig. 21
Block diagram of timers 1 to 3 (
φ
is internal system clock)
Timer 1
The count source of timer 1 is the output of timer 123 pre-divider.
The division ratio of the pre-divider can be selected by the pre-
divider division ratio bits of timer 123 mode register (T123M). Refer
to Timer 123 mode register configuration (f is internal system clock).
On a timer 1 underflow, the timer 1 interrupt request bit will be set to
“1”.
Writing to timer 1 initializes the latch and counter.
Timers 2 and 3
The count source of timers 2 and 3 can be either the output of the
timer 123 pre-divider or the timer 1 underflow. The count source can
be selected by the timer count source selection bits of timer 123
mode register (T123M).
Writing to timer 2 register affects the reload latch only or both of the
reload latch and counter depending on the timer 2 write control bit
of T123M. When the timer write control bit is set to “0”, both latch
and counter will be initialized simultaneously; when set to “1” only
the reload latch will be initialized, on an underflow, the counter will
be set to the modified reload value. Writing to timer 3 initializes
latch and counter both.
Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit
to be set to “1”.
T123M
0
1
1/8
1/32
1/128
T123M
67
φ
T1 counter (8)
T1 latch (8)
T2 counter (8)
T2 latch (8)
T3 counter (8)
T3 latch (8)
T1 interrupt
T2 interrupt
T3 interrupt
S
R
Q
S
R
Q
T123M
3
T123M
4
T123M
1
T123M
1
S
T
Q
P1
6
/PWM
P1
6
latch
P1D
6
T123M
1
“00
“01”
“10”
“11”
“1”
“0”
“0”
“1”
“1”
“0”
“0”
“1”
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