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參數(shù)資料
| 型號： | 74F760 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal buffer (open-collector)(八通道緩沖器（集電極開路）) |
| 中文描述： | 八路緩沖器（集電極開路）（八通道緩沖器（集電極開路）） |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 128K |
| 代理商： | 74F760 |
Philips Semiconductors
Application note
AN214
74F extended octal-plus family applications
June 1988
8
be transferred either from the A
N
port register to the B
N
port outputs
or from the B
N
port register to the A
N
port outputs.
The same capabilities are available to data presented to the B–port.
When a port’s output buffers are enabled (OE = LOW and
DIR = LOW for A
N
outputs enabled or HIGH for B
N
outputs
enabled), the SXX select inputs (SAB and SBA) control the two
EX-OR gates allowing the output port data to come either directly
from the other port (real-time transfer) or from the other port’s input
storage register.
The CPABN and CPBA inputs are the LOW-to-HIGH edge-triggered
clock inputs for the A
N
port register and B
N
port register. Data
presented to either port’s inputs can be clocked into its input register
on a LOW-to-HIGH CPXX input regardless of the logic levels on any
of the other mode control inputs.
The 74F651A–654A’s OEAB and OEBA output enable inputs may
be tied together to enable the B outputs when HIGH or A
N
outputs
when held LOW or can be used separately to independently control
the two output ports. Tying the 74F651A–654A’s OEAB and OEBA
together is logically equivalent to the DIR input of the
74F646A–649A.
Parity Bus Series Advantages
The increased functional density of the Parity Bus Series produces a
2:1 package reduction (plus 1 AND gate) and, therefore, 38:24 pin
reduction. Power dissipation savings of 82.5mW for the
74F455/456/655A/656A Drivers and 137.5mW for the 74F657 are
also achieved through shared internal logic. Table 2 shows the
package/pin advantage as well as the worst case propagation
delays and I
CC
of the Family versus their competition.
Figure 9 is a summary of the pin configurations of the entire Parity
Bus Drivers and Transceiver Series.
The 74F455/456/655A/656A Octal Parity Bus Drivers and the
74F657 Octal Parity Bus Transceiver Series combines the popular
Philips Semiconductors 74F24X buffer/transceiver functions with the
74F280B 9-bit Parity Generator/Checker, “Broadside” input/output
pin configurations, “Light-Load” inputs and an increased guaranteed
sink/source capabilities of –15mA/64mA for low impedance bus
environments. The 74F445/446 Drivers with their multiple
center-package ground supply pins are logically identical to the
74F655A/656A Drivers, except for the latter’s single corner-package
supply pins and an additional Output Enable input. The 74F657
Parity Bus Transceiver allows the parity to be generated and
checked in both directions in a single package replacing one 74F245
Transceiver, 20-pin DIP and two 74F280, 16-pin DIPs plus a couple
of gates.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OE1
OE2
PI
I0
I1
I2
V
CC
I3
I4
I5
I6
I7
OE1
OE3
PI
I0
GND
T/R
A0
A1
A2
A3
A4
V
CC
A5
A6
A7
O/E
ERROR
OE
B0
B1
B2
B3
GND
GND
B4
B5
B6
B7
PARITY
V
CC
OE2
Y0/Y0
Y1/Y1
Y2/Y2
Y3/Y3
Y4/Y4
Y5/Y5
Y6/Y6
Y7/Y7
Σ
O
Σ
E
Xcvr
F657
S
Buffer
F655/6A
Buffer
F455/6
Buffer
F455/6
Buffer
F655/6A
Xcvr
F657
I1
I2
I3
I4
I5
I6
I7
Σ
O
Σ
E
Y0/Y0
Y1/Y1
Y2/Y2
GND
GND
Y3/Y3
Y4/Y4
Y5/Y5
Y6/Y6
Y7/Y7
SF01336
Figure 9. 74F Octal Parity Drivers/Transceiver Pin Configurations
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| 74F764-1N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DRAM dual-ported controllers |
| 74F765-1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DRAM dual-ported controllers |
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