- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360443 > 74F760 (NXP Semiconductors N.V.) Octal buffer (open-collector)(八通道緩沖器（集電極開路）) PDF資料下載
參數(shù)資料
| 型號： | 74F760 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal buffer (open-collector)(八通道緩沖器（集電極開路）) |
| 中文描述： | 八路緩沖器（集電極開路）（八通道緩沖器（集電極開路）） |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 128K |
| 代理商： | 74F760 |
Philips Semiconductors
Application note
AN214
74F extended octal-plus family applications
June 1988
3
SF01331
D5
D6
R1
6K
D4
Q1
Q1A
Q2
Y
IN
D3
V
CC
R6
6K
R5
5K
R4
50
Q5
R2
50
R3
10K
Q3
Q4
D2
D1
Q6
R8
2K
Q7
R7
7.5K
D7
Q8
R9
2.8K
Q9
Q10
D8
D9
EN
R10
2.8K
R11
2.8K
Q12
D10
R12
500
R13
10K
D11
Q11
Q13
R14
D13
D12
Y
OUT
I
OL
options:
1) If I
OH
/I
OL
=
R14
R11
R10
R12
2) If I
OH
/I
OL
=
R14
R11
R10
R12
–15/64 mA
12
2.8K
2.8K
500
–3/24 mA
30
5K
5K
2K
=
=
=
=
=
=
=
=
Figure 3. 74F455 Buffer/Drive Cell Circuit Diagram
The 8-, 9-, and 10-bit Series 24-pin Solution
Whether your system requires an 8–, 9-, or 10-bit bus interface, the
Extended Octal-Plus Family has standardized solutions in
24-pin/Slim-DIP/Broadside input/output packages with corner power
supply pins (12 & 24) and standard designations for common control
functions located at or near the package corners. Octals offer more
mode control inputs than do the 9- or 10-bit products. Virtually all
family devices with 3-State outputs are guaranteed to source/sink
–15/64mA @ V
OH
/V
OL
= 2.0/0.55V (except for the 74F841–846
Latched Drivers, which are spec’ed at –15mA/48mA). The A
N
port
outputs of several of the family’s transceivers are guaranteed to
supply –3mA/48mA).
The Octal Parity Bus Series offers several notable exceptions to the
above standard pinouts. This series has three parts with two
center-package ground pins to minimize ground-bounce noise. All
outputs (except the A
N
port of the 74F657 Parity Bus Transceiver
spec’ed at –3mA/24mA) are guaranteed to source/sink more than
–15mA/64mA.
Current PC board, multi-layer technology make is possible to take
into consideration the physical location of input/output pins,
transmission line characteristics and supply power distribution.
Lining up all inputs and output on opposite sides of the package
allows the address, data and control bus signal to flow in a direct
physical path from the
μ
P CPU through the bus interface chips and
onto the appropriate bus. This “broadside” bus design approach
produces very clean PC board layouts and may, in fact eliminate
and entire PC board interconnection layer. Standardization of power
supply, mode control and input/output pins, whether 8-, 9-, or 10-bit
bus functions, permits simplified, structured PC board layout.
Input Structures
Referring to Figure 3, the 74F455 Inverting Buffer/Driver Cell Circuit
Diagram is an example of the family’s input and output circuitry. The
patented Philips Semiconductors “Light-Load” NPN input structure
(Q1/23/4/5, R1/2/3/4/5/6 and D4) and turn-OFF speed-up circuit (Q2
and D2/3) are used throughout the 74F Extended Octal-Plus Family.
the “Light-Load” NPN input is actually a high speed, differential
amplifier with the reference side, the anode of D4, clamped at two
diode voltage drops above ground (BE junctions of Q8/9/10 and Q
11 of
1.4V at 25
°
C). When the V
IH
rises above this clamp voltage,
the BE junction of Q1 is forward based allowing beta amplified, CE
current to flow into the <1.0mA constant current source, Q3 (driven
by Q4/5 and R2/3/4/5/6). The beta of Q1 is guaranteed, by design,
to be >50, thereby guaranteeing that the input base bias current will
be <20
μ
A. The emitter of Q1 rises to 1V
BE
(
V
IH
, reverse biasing D4 and permitting C8/9/10 base bias current to
flow through R1.
300mV) below the
The patented turn-OFF circuit consisting of Q2 and D2/3 produces a
dynamic speed to help turn Q8/9/10 OFF quickly. During the time
that the Q1 is turned-ON (input = V
IH
>2.0V), the revers-biased
Schottky diode, D2, acting as a capacitor, will be charged to the
voltage at the emitter of Q1A or 1V
BE
voltage drop below the input
(>2.0 – 1V
BE
). When the input is switched to <V
IL
(or <0.8V), the D2
stored charge discharges through the BE of Q2. Q2 CE current
through D3 rapidly turns Q8/9/10 OFF.
These circuit innovations produce high performance, very low input
bias current (
±
20
μ
A) gate inputs. This input leakage represents a
30X reduction over the standard 74F family’s 600
μ
A input current
with virtually no loss in speed. The 74F Extended Octal-Plus
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F30244 | Octal 30Ω line driver with enable,non-inverting (open collector)(帶使能30Ω的八線驅(qū)動器，同向（開啟集電極）) |
| 74F764-1 | DRAM dual-ported controllers |
| 74F764-1A | DRAM dual-ported controllers |
| 74F764-1N | DRAM dual-ported controllers |
| 74F765-1 | DRAM dual-ported controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F760D | 制造商:SIG 功能描述: |
| 74F764-1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DRAM dual-ported controllers |
| 74F764-1A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DRAM dual-ported controllers |
| 74F764-1N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DRAM dual-ported controllers |
| 74F765-1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DRAM dual-ported controllers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。