參數(shù)資料
型號： 74F760
廠商： NXP Semiconductors N.V.
英文描述： Octal buffer (open-collector)(八通道緩沖器（集電極開路）)
中文描述： 八路緩沖器（集電極開路）（八通道緩沖器（集電極開路））
文件頁數(shù)： 13/14頁
文件大?。?/td> 128K
代理商： 74F760
Philips Semiconductors
Application note
AN214
74F extended octal-plus family applications
June 1988
13
Table 3. The Extended Octal-Plus Family Capabilities Summary
Part
Number
#
Bits
Polarity
Output
Broad-
side
I
OH
/I
OL
MIN
Storage
Speed
Parity
Comments
“Light-Load” buffer and Line Driver Functions
74F455/456
8-bit
INV/NINV
3-St
Yes
–15/64mA
None
7.5ns
Yes
Multiple/Ctr Pkg. GND Pins,
Σ
E
,
Σ
O
= –15/64mA
74F540/541
8-bit
INV/NINV
3-St
Yes
–15/64mA
None
7.5ns
No
Broadside pinout of 74F240
74F655A/656A
8-bit
INV/NINV
3-St
Yes
–15/64mA
None
7.5ns
Yes
Σ
E
,
Σ
O
= –15/64mA
74F827/828
10-bit
NINV/INV
3-St
Yes
–15/64mA
None
9.0ns
No
“Light-Load” Register and Latch Functions
74F821/822
10-bit
NINV/INV
3-St
Yes
–15/64mA
Reg
100MHz
No
Data, MR, OE, & Clock EN Inputs
74F823/824
9-bit
NINV/INV
3-St
Yes
–15/64mA
Reg
100MHz
No
Data, MR, OE, & Clock EN Inputs
74F825/826
8-bit
NINV/INV
3-St
Yes
–15/64mA
Reg
100MHz
No
Data, MR, OE, & Clock EN Inputs
74F841/842
10-bit
NINV/INV
3-St
Yes
–15/48mA
Latch
100MHz
No
Data, MR, OE, & LE Enable Inputs
74F843/844
9-bit
NINV/INV
3-St
Yes
–15/48mA
Latch
100MHz
No
Data, MR, OE, & LE Enable Inputs
74F845/846
8-bit
NINV/INV
3-St
Yes
–15/48mA
Latch
100MHz
No
Data, MR, OE, & LE Enable Inputs
“Light-Load” Transceiver Functions
74F545
8-bit
NINV
A
N
3-St
B
N
3-St
Yes
Yes
–3/24mA
–15/64mA
None
None
7.0ns
7.0ns
No
No
74F550/551
8-bit
NINV/INV
B
N
3-St
A
N
3-St
Yes
Yes
–15/64mA
–3/24mA
B
N
-Reg
A
N
-Reg
10.5ns
10.5ns
No
No
A
N
→
B
N
, ERROR, status registers, 50MHz
B
N
→
A
N
, Multiple/Center Pkg. GND pins **
74F552
8-bit
NINV
B
N
3-St
A
N
3-St
Yes
Yes
–15/64mA
–3/24mA
B
N
-Reg
A
N
-Reg
10.5ns
10.5ns
Yes
Yes
A
N
→
B
N
, PARITY, ERROR, status registers
B
N
→
A
N
, Multiple/Center Pkg. GND pins **
74F588
8-bit
NINV
A
N
= 3-St
B
N
3-St
Yes
Yes
–3/24mA
–15/64mA
None
None
7.5ns
7.5ns
No
No
IEEE-488/GPIB w/line term. resistors
74F620/623
8-bit
INV/NINV
B
N
3-St
A
N
3-St
Yes
Yes
–15/64mA
–3/24mA
None
None
7.5ns
7.5ns
No
No
A
N
→
B
N
B
N
→
A
N
74F621/622
8-bit
NINV/INV
B
N
OC
A
N
OC
Yes
Yes
OC/64mA
OC/24mA
None
None
13.0ns
12.5ns
No
No
A
N
→
B
N
B
N
→
A
N
74F640
8-bit
INV
A/B 3-St
Yes
–15/64mA
None
7.5ns
No
A
N
B
N
74F641/642
8-bit
NINV/INV
B
N
OC
A
N
OC
Yes
Yes
OC/64mA
OC/20mA
None
None
13.0ns
12.0ns
No
No
A
N
→
B
N
B
N
→
A
N
74F646A/648A
8-bit
NINV/INV
A/B 3-St
Yes
–15/48mA
2 Reg
11.0ns
No
A
N
B
N
, registers for A
N
& B
N
ports, 80MHz (min.)
74F647/649
8-bit
NINV/INV
AB OC
Yes
OC/64mA
2 Reg
19.5ns
No
A
N
B
N
, registers for A
N
& B
N
ports, 40MHz (min.)
74F651A/652A
8-bit
INV/NINV
A/B 3-St
Yes
–15/48mA
2 Reg
11.5ns
No
A
N
B
N
, registers for A
N
& B
N
ports, 80MHz (min.)
74F653/654
8-bit
NINV/INV
B
N
3-St
A
N
OC
Yes
Yes
–15/64mA
OC/64mA
B
N
-Reg
A
N
-Reg
11.0ns
20.0ns
No
No
A
N
→
B
N
, B
N
port = 85MHz (min.)
B
N
→
A
N
, A
N
port = 45MHz (min.)
74F657
8-bit
NINV
B
N
3-St
A
N
3-St
Yes
Yes
–15/64mA
–3/24mA
None
None
8.0ns
8.0ns
Yes
No
A
N
→
B
N
, PARITY, ERROR = –15/64mA
B
N
→
A
N
, Multiple/Center Pkg. GND pins
74F861/862
10-bit
NINV/INV
A/B 3-St
Yes
–15/64mA
None
10.0ns
No
A
N
B
N
74F863/864
9-bit
NINV/INV
A/B 3-St
Yes
–15/64mA
None
10.0ns
No
A
N
B
N
74F1245
8-bit
NINV
B
N
3-St
A
N
3-St
Yes
Yes
–15/64mA
–3/24mA
None
None
8.0ns
8.0ns
No
No
A
N
→
B
N
, “Light-Load” pin-for-pin ’F245 replacement
B
N
→
A
N
74F2951/2952
NOTES:
All parameters are worst-case, unless otherwise specified.
3-St
=
3-State
OC
=
Open Collector
Reg
=
LOW-to-HIGH edge clocked D-type register
Latch =
HIGH logic level on the Latch Enable logic, data passes directly through D-type latch,
HIGH-to-LOW logic level transition of the Latch Enable, data is stored in the D-type latch.
**
=
These devices utilize standard FAST input structures producing input currents of +20
μ
A and –0.6mA.
MR
=
Master Reset
OE
=
Output Enable
8-bit
INV/NINV
A/B 3-St
Yes
–15/64mA
2 Reg
12.5ns
No
A
N
B
N
, registers for A
N
& B
N
ports, 80MHz (min.) **
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