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參數(shù)資料
| 型號(hào)： | 73S1217F-68MR/F/PE |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 45/140頁 |
| 文件大小： | 0K |
| 描述： | IC SOC SMART CARD READER 68QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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DS_1217F_002
73S1217F Data Sheet
PGADDR register, added “Note: the page address is shifted left by one bit
(see detailed description above).”
In Table 3, changed “FLSHCRL” to “FLSHCTL”.
In Table 5, removed the PREBOOT bit description.
In Table 5, moved the TRIMPCtl bit description to FUSECtl and moved the
FUSECtl bit description to TRIMPCtl.
In Table 6, changed “PGADR” to “PGADDR”.
In Table 7, added PGADDR.
In Table 8, changed the reset value for RTCCtl from “0x81” to “0x00”.
Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,
LEDCal and LOCKCtl registers.
In Table 11, removed Mcount entries 7, 8, 9 and 10.
In Figure 4, removed CPUCLK.
In Table 22, corrected the descriptions for TCON.2 and TCON.0.
In the Miscellaneous Control Register 1 (MISCtl1) description, added two
paragraphs about MPU clock rates of 12MHz or greater, changing the
MPU clock rate or the number of wait states.
Changed the register address for ATRMsB from FE21 to FE1F.
In Section 1.7.17.5, deleted “The ETU clock is held in reset condition until
the activation sequence begins (either by VCCOK=1 or VCCTMR timeout)
and will go high the ETU period thereafter.”
In Section 1.7.17.5, added “Synchronous card operation is broken down
into three primary types. These are commonly referred to as 2-wire, 3-
wire and I2C synchronous cards. Each card type requires different control
and timing and therefore requires different algorithms to access. Teridian
has created an application note to provide detailed algorithms for each
card type. Refer to the application note titled 73S12xxF Synchronous
Card Design Application Note
.”
In Table 85 and Table 114, changed the SYCKST bit to I2CMODE.
Replaced Figure 23, Figure 24, and Figure 25 with new timing diagrams.
In Table 114, replaced SYCKST (STXCtl, bit 7) with I2CMODE and
SCISYN (SPrtcol, bit 7) with I2CMODE.
In Figure 27 and Figure 28, replaced the schematics with new schematics.
In Section 3.4, changed the Fxtal Min value from 4 to 6.
Formatted the document per new standard. Added section numbering.
Rev. 1.2
139
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73S1217F-EB | 功能描述:開發(fā)板和工具包 - 8051 73S1217F Eval Brd (Usb Cable, Doc. Cd) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 73S1217F-EB-Lite | 功能描述:開發(fā)板和工具包 - 8051 73S1217F EVB Lite w/Plug & Play/Usb RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 73S1217F-IMR/F | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More |
| 73S13B | 制造商:QUARTZCOM 制造商全稱:QUARTZCOM the communications company 功能描述:-20 ~ +70 °C commercia l application -30 ~ +75 °C on request |
| 73S5040G01X0A | 制造商:NEX Computers 功能描述:INTEL 40GB SSD - Bulk |
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