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| 型號(hào)： | 73S1217F-68MR/F/PE |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 140/140頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SOC SMART CARD READER 68QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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DS_1217F_002
73S1217F Data Sheet
Rev. 1.2
99
Smart Card Control Register (SCCtl): 0xFE0A
0x21
This register is used to monitor reception of data from the smart card.
Table 89: The SCCtl Register
MSB
LSB
RSTCRD
–
IO
IOD
C8
C4
CLKLVL
CLKOFF
Bit
Symbol
Function
SCCtl.7
RSTCRD
1 = Asserts the RST (set RST = 0) to the smart card interface, 0 = De-
assert the RST (set RST = 1) to the smart card interface. Can be used to
extend RST to the smart card. Refer to the RLength register description.
This bit is operational in all modes and can be used to extend RST during
activation or perform a “Warm Reset” as required. In auto-sequence mode,
this bit should be set = 0 to allow the sequencer to de-assert RST per the
RLength parameters.
In sync mode (see the SPrtcol register) the sense of this bit is non-inverted,
if set =1 , RST = 1, if set = 0, RST = 0. Rlen has no effect on Reset in sync
mode.
SCCtl.6
–
SCCtl.5
IO
Smart Card I/O. Read is state of I/O signal (Caution, this signal is not
synchronized to the MPU clock). In Bypass mode, write value is state of
signal on I/O. In sync mode, this bit will contain the value of I/O pin on the
latest rising edge of CLK.
SCCtl.4
IOD
Smart Card I/O Direction control Bypass mode or sync mode. 1 = input
(default), 0 = output.
SCCtl.3
C8
Smart Card C8. When C8 is an output, the value written to this bit will
appear on the C8 line. The value read when C8 is an output is the value
stored in the register. When C8 is an input, the value read is the value on
the C8 pin (Caution, this signal is not synchronized to the MPU clock).
When C8 is an input, the value written will be stored in the register but not
presented to the C8 pin.
SCCtl.2
C4
Smart Card C4. When C4 is an output, the value written to this bit will
appear on the C4 line. The value read when C4 is an output is the value
stored in the register. When C4 is an input, the value read is the value on
the C4 pin (Caution, this signal is not synchronized to the MPU clock).
When C4 is an input, the value written will be stored in the register but not
presented to the C4 pin.
SCCtl.1
CLKLVL
1 = High, 0 = Low. If CLKOFF is set = 1, the CLK to smart card will be at
the logic level indicated by this bit. If in bypass mode, this bit directly
controls the state of CLK.
SCCtl.0
CLKOFF
0 = CLK is enabled. 1 = CLK is not enabled. When asserted, the CLK will
stop at the level selected by CLKLVL. This bit has no effect if in bypass
mode.
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