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參數(shù)資料
| 型號(hào)： | 73S1217F-68MR/F/PE |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 124/140頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SOC SMART CARD READER 68QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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73S1217F Data Sheet
DS_1217F_002
> EGT
< WWT
CHAR 1
CHAR 2
CHAR
N+1
CHAR
N+2
CHAR
N+3
BLOCK1
BLOCK2
> BWT
< CWT
RECEPTION
TRANSMISSION
T = 1 Mode
CHAR 1
CHAR 2
CHAR N
RST
TSTO(7:0)
ATRTO(15:0)
VCC_OK
RLen(7:0)
CHAR 1
CHAR 2
CHAR N
ATR Timing Parameters
IWT(15:0)
BGT(4:0)
TX
T = 0 Mode
IO
EGT
(By seting Last_TXByte and
TX/RXB=0 during CHAR N,
RX mode will start after last
TX byte)
WWT is set by the value in the BWT registers.
Figure 21: Guard, Block, Wait and ATR Time Definitions
1.7.17.4
Bypass Mode
It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart
cards. This is called Bypass mode. In this mode the embedded firmware will communicate directly with
the selected smart card and drive I/O during transmit and read I/O during receive in order to communicate
with the smart card. In this mode, ATR processing is under firmware control. The firmware must
sequence the interface signals as required. Firmware must perform TS processing, parity checking,
break generation and CRC/LRC calculation (if required).
1.7.17.5
Synchronous Operation Mode
The 73S1217F supports synchronous operation. When sync mode is selected for either interface, the
obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the
interface must be selected to obtain a smart card clock signal. In sync mode, input data is sampled on
the rise of CLK, and output data is changed on the fall of CLK.
Special Notes Regarding Synchronous Mode Operation
84
Rev. 1.2
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| 73S1217F-EB | 功能描述:開(kāi)發(fā)板和工具包 - 8051 73S1217F Eval Brd (Usb Cable, Doc. Cd) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
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