參數(shù)資料
型號: 72SD3232RPFE
廠商: MAXWELL TECHNOLOGIES
元件分類: DRAM
英文描述: 1 Gbit SDRAM 32-Meg X 32-Bit X 4-Banks
中文描述: 32M X 32 SYNCHRONOUS DRAM, 6 ns, DFP72
封裝: STACK, DFP-72
文件頁數(shù): 8/41頁
文件大小: 596K
代理商: 72SD3232RPFE
72SD3232
M
8
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
02.04.05 Rev 3
Command Operation
Command Truth Table
The SDRAMrecognizes the following commands specified by the CS, RAS, CAS, WE and address pins:
Note: H: V
IH
L: V
IL
x V
IH
or V
IL
V: Valid address input
Ignore command (DESL):
When this command is set (CS = High), the SDRAMignores command input at
the clock. However the internal status is held.
No Operation (NOP):
This command is not an execution command. However the internal operations
continue.
Column address strobe and read command (READ):
This command starts a read operation. In addition,
the start address of a burst read is determned by the column address (AY0 to AY9) and the bank select
address (BS). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge (READ A):
This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4, or 8.
C
OMMAND
S
YMBOL
N
-1
N
CS
RAS
CAS
WE
BA0/
BA1
A10
A0
TO
A12
Ignore command
No Operation
Column Address and
Read command
Read with auto-pre-
charge
Column Address and
write command
Write with auto-pre-
charge
Row address strobe
and bank active
Precharge select
bank
Precharge all banks
Refresh
DESL
NOP
READ
H
H
H
x
x
x
H
L
L
x
H
H
x
H
L
x
H
H
x
x
V
x
x
L
x
x
V
READ A
H
x
L
H
L
H
V
H
V
WRIT
H
x
L
H
L
L
V
L
V
WRIT A
H
x
L
H
L
L
V
H
V
ACTV
H
x
L
L
H
H
V
V
V
PRE
H
x
L
L
H
L
V
L
x
PALL
REF/
SELF
MRS
H
H
x
L
L
L
L
L
H
L
L
H
x
x
H
x
x
x
Mode register set
H
x
L
L
L
L
V
V
V
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