參數(shù)資料
型號(hào): 72SD3232RPFE
廠商: MAXWELL TECHNOLOGIES
元件分類: DRAM
英文描述: 1 Gbit SDRAM 32-Meg X 32-Bit X 4-Banks
中文描述: 32M X 32 SYNCHRONOUS DRAM, 6 ns, DFP72
封裝: STACK, DFP-72
文件頁數(shù): 15/41頁
文件大?。?/td> 596K
代理商: 72SD3232RPFE
72SD3232
M
15
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
02.04.05 Rev 3
From PRECHARGE state, command operation
To [DESL], [NOP]:
When these commands are executed, the SDRAMenters the IDLE state after t
RP
has
elapsed fromthe completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [PRE], or [PALL]:
These commands result in no operation.
To [ACTV]:
The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]:
The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]:
The synchronous DRAMenters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]:
These commands result in no operation.
To [READ], [READ A]:
A read operation starts. (However, an interval of t
RCD
is required.)
To [WRIT], [WRIT A]:
A write operation starts. (However, an interval of t
RCD
is required.)
Write with auto-
precharge
H
x
x
x
x
DESL
Continue burst to end and pre-
charge
Continue burst to end and pre-
charge
ILLEGAL
1
ILLEGAL
1
Other bank active
ILLEGAL on same bank
4
ILLEGAL
1
ILLEGAL
ILLEGAL
Enter IDLE after t
RC
Enter IDLE after t
RC
ILLEGAL
3
ILLEGAL
3
ILLEGAL
3
ILLEGAL
3
ILLEGAL
ILLEGAL
L
H
H
H
x
NOP
L
L
L
H
H
L
L
L
H
H
L
H
BA, CA, A10
BA, CA, A10
BA, RA
READ/READ A
WRIT/WRIT A
ACTV
L
L
L
H
L
L
L
L
L
L
L
L
L
L
x
H
H
H
L
L
L
L
H
L
L
x
H
L
L
H
H
L
L
L
H
L
x
H
H
L
H
L
H
L
BA, A10
x
MODE
x
x
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
x
MODE
PRE, PALL
REF, SELF
MRS
DESL
NOP
READ/READ A
WRIT/WRIT A
ACTV
PRE, PALL
REF, SELF
MRS
Refresh ( auto-
refresh)
1. Illegal for same bank, except for another bank
2. NOP for same bank, except for another bank
3. Illegal for all banks
4. If t
RRD
is not satisfied, this operation is illegal
5. An interval of t
DPL
is required between the final valid data input and the precharge command
C
URRENT
S
TATE
CS
RAS
CAS
WE
A
DDRESS
C
OMMAND
O
PERATION
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