參數(shù)資料
型號(hào): 72SD3232RPFE
廠商: MAXWELL TECHNOLOGIES
元件分類: DRAM
英文描述: 1 Gbit SDRAM 32-Meg X 32-Bit X 4-Banks
中文描述: 32M X 32 SYNCHRONOUS DRAM, 6 ns, DFP72
封裝: STACK, DFP-72
文件頁數(shù): 10/41頁
文件大小: 596K
代理商: 72SD3232RPFE
72SD3232
M
10
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
02.04.05 Rev 3
DQM1 - DQM4 Truth Table
Note: H: V
IH
L: V
IL
x V
IH
or V
IL
Write: I
DID
is Needed
Read: I
DOD
is Needed
The SDRAMcan mask input/output data by means of DQM1- DQM4.
During reading, the output buffer is set to Low-Z by setting DQM1 - DQM4 to Low enabling data output. On
the other hand, when DQM1 - DQM4 are set High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQM1 - DQM4 to Low When DQM1 - DQM4 is set to High, the
previous data is held ( the new data is not written). Desired data can be masked during burst read or burst
write by setting DQM1 - DQM4. For more details, refer to the DQM1 - DQM4 control section of the SDRAM
operating instructions.
C
OMMAND
S
YMBOL
CKE =
N-1
CKE =
N
DQM4
DQM3
DQM2
DQM1
(DQ248 to DQ31) write enable/output enable
(DQ248 to DQ31) write inhibit/output disable
(DQ16 to DQ24) write enable/output enable
(DQ16 to DQ24) write inhibit/output disable
(DQ8 to DQ15) write enable/output enable
(DQ8 to DQ15) write inhibit/output disable
(DQ0 to DQ7) write enable/output enable
(DQ0 to DQ7) write inhibit/output disable
ENB4
MASK4
ENB3
MASK3
ENB2
MASK2
ENB1
MASK1
H
H
H
H
H
H
H
H
x
x
x
x
x
x
x
x
H
L
x
x
x
x
x
x
x
x
H
L
x
x
x
x
x
x
x
x
H
L
x
x
x
x
x
x
x
x
H
L
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