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參數(shù)資料
| 型號： | 7130LA35TF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 1K X 8 DUAL-PORT SRAM, 35 ns, PQFP64 |
| 封裝： | STQFP-64 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 153K |
| 代理商： | 7130LA35TF8 |
13
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).
2.
CEL = CER = VIL
3.
OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(3)
NOTES:
1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2.
BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
BUSY"B"
2689 drw 13
R/
W"A"
tWP
tWH
tWB
R/
W"B"
(2)
(1)
,
tWC
tWP
tDW
tDH
tBDD
tDDD
tBDA
tWDD
ADDR"B"
DATAOUT"B"
DATAIN"A"
ADDR"A"
MATCH
VALID
MATCH
VALID
R/
W"A"
BUSY"B"
tAPS
(1)
2689 drw 12
tBAA
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| 7130LA35TFG | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 8KBIT 35NS 64TQFP |
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