參數(shù)資料
型號: 70T9169L12PF8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 16K X 9 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 6/16頁
文件大?。?/td> 252K
代理商: 70T9169L12PF8
6.42
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
14
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0 = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from An to An +1. The transition shown indicates the time required for the counter to advance. The An +1 Address is written
to during this cycle.
ADDRESS
An
CLK
DATAIN
Dn
Dn + 1
Dn + 2
ADS
CNTEN
tCH2
tCL2
tCYC2
5654 drw 17
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
tSA
tHA
tSAD tHAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
tSD tHD
ADDRESS
An
D0
tCH2
tCL2
tCYC2
Q0
Q1
0
CLK
DATAIN
R/
W
CNTRST
5654 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
tSRST tHRST
tSD
tHD
tSW tHW
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATAOUT
tSA tHA
1
An
An + 1
(5)
(6)
Ax
(4)
(6)
.
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