參數(shù)資料
型號(hào): 70T9169L12PF8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 16K X 9 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 13/16頁(yè)
文件大小: 252K
代理商: 70T9169L12PF8
6.42
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)
70T9169/59L7
Com’l Only
70T9169/59L9
Com’l & Ind
70T9169/59L12
Com’l Only
Symbol
Parameter
Test Condition
Version
Typ.
(4)
Max.
Typ.
(4)
Max.
Typ.
(4)
Max.
Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM’L
L
80
200
75
175
70
150
mA
IND
L
____
75
220
____
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM’L
L
20
60
20
50
20
40
mA
IND
L
____
20
70
____
ISB2
Standby
Current (One
Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(5)
Active Port Outputs
Disabled, f=fMAX
(1)
COM’L
L
50
115
47
100
45
85
mA
IND
L
____
47
190
____
ISB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports
CEL and
CER >VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM’L
L
0.13.0
mA
IND
L
____
0.1
3.0
____
ISB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
VIN < 0.2V, Active Port,
Outputs Disabled , f = fMAX
(1)
COM’L
L
50
115
47
100
45
85
mA
IND
L
____
47
190
____
5654 tbl 09
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VDD = 2.5V ± 100mV)
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Symbol
Parameter
Test Conditions
70T9169/59L
Unit
Min.
Max.
|ILI|
Input Leakage Current(1)
VDD = 2.6V, VIN = 0V to VDD
___
5A
|ILO|
Output Leakage Current
CE = VIH or CE1 = VIL, VOUT = 0V to VDD
___
5A
VOL
Output Low Voltage
IOL = +2mA
___
0.4
V
VOH
Output High Voltage
IOH = -2mA
2.0
___
V
5654 tbl 08
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 2.5V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 75mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX
= VIH means CE0X = VIH or CE1X = VIL
CEX
< 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX
> VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
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