參數(shù)資料
型號: 70T9169L12PF8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 16K X 9 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 4/16頁
文件大小: 252K
代理商: 70T9169L12PF8
6.42
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
5654 drw 13
Qn
DATAOUT
tCD1
Qn + 1
tSD tHD
tCD1
tDC
tCKHZ
Qn + 3
tCD1
tDC
tSW tHW
tSA
tHA
READ
NOP
READ
tCKLZ
(4)
(2)
(1)
tSW tHW
WRITE
(5)
CE0
CLK
CE1
tCH1
tCL1
tCYC1
tSC
tHC
R/
W
ADDRESS
An
An +1
tSW tHW
An + 2
An + 3
An + 4
An + 5
(4)
DATAIN
Dn + 2
5654 drw 14
Qn
DATAOUT
tCD1
tSD tHD
tCD1
tDC
Qn + 4
tCD1
tDC
tSW tHW
tSA
tHA
READ
WRITE
READ
tCKLZ
(2)
Dn + 3
tOHZ
(1)
OE
tOE
CE0
CLK
CE1
tCH1
tCL1
tCYC1
tSC tHC
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