參數(shù)資料
型號(hào): 70T9169L12PF8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 16K X 9 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 1/16頁
文件大?。?/td> 252K
代理商: 70T9169L12PF8
2004 Integrated Device Technology, Inc.
AUGUST 2004
DSC-5654/2
1
Functional Block Diagram
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
Commercial:7.5/9/12ns(max.)
Industrial: 9ns (max.)
Low-power operation
IDT70T9169/59L
Active: 225mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
4.0ns setup to clock and 0.5ns hold on all control, data, and
addressinputs
Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timedwriteallowsfastcycletime
12ns cycle time, 83MHz operation in Pipelined output mode
LVTTL- compatible, single 2.5V (±100mV) power supply
Industrial temperature range (40°C to +85°C) is
available for 66MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
HIGH-SPEED 2.5V
16/8K X 9 SYNCHRONOUS
PIPELINED
DUAL-PORT STATIC RAM
IDT70T9169/59L
0
1
0/1
1
0/1
0
R/
WR
OER
CE0R
CE1R
FT/PIPER
I/O
Control
MEMORY
ARRAY
Counter/
Address
Reg.
I/O
Control
5654 drw 01
A13R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
A0L
CLKL
ADSL
A13L(1)
CNTENL
CNTRSTL
Counter/
Address
Reg.
R/
WL
CE0L
OEL
CE1L
I/O0L -I/O8L
I/O0R -I/O8R
1
0/1
0
1
0/1
FT/PIPEL
NOTE:
1. A13 is a NC for IDT70T9159.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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