68HC(9)12DG128 Rev 1.0
MOTOROLA
General Description
11
General Description
General Description
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
68HC(9)12DG128 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Introduction
The 68HC(9)12DG128 microcontroller unit (MCU) is a 16-bit device
composed of standard on-chip peripherals including a 16-bit central
processing unit (CPU12), 128K bytes of flash EEPROM
(68HC912DG128) or 128K bytes ROM (68HC12DG128), 8K bytes of
RAM, 2K bytes of EEPROM, two asynchronous serial communication
interfaces (SCI), a serial peripheral interface (SPI), an inter-IC interface
(I2C), an enhanced capture timer (ECT), two 8-channel,10-bit
analog-to-digital converters (ATD), a four-channel pulse-width
modulator (PWM), and two CAN 2.0 A, B software compatible modules
(MSCAN12). System resource mapping, clock generation, interrupt
control and bus interfacing are managed by the lite integration module
(LIM). The 68HC(9)12DG128 has full 16-bit data paths throughout,
however, the external bus can operate in an 8-bit narrow mode so single
8-bit wide memory can be interfaced for lower cost systems. The
inclusion of a PLL circuit allows power consumption and performance to
be adjusted to suit operational requirements. In addition to the I/O ports
available in each module, 16 I/O port pins are available with
Key-Wake-Up capability from STOP or WAIT mode.
1-gen