MC68HC05B6
Rev. 4
MOTOROLA
E-5
MC68HC705B16
14
E.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see
Figure D-2). The t
OXOV
or t
ILCH
specifications (see Section E.8) do not apply when using an
external clock input. The equivalent specification of the external clock source should be used in
lieu of t
OXOV
or t
ILCH
.
E.3
EPROM
The MC68HC705B16 memory map is given in Figure E-2. The device has a total of 15168 bytes
of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM.
The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the
user’s software would be loaded into a programming board where V
PP6
is controlled by one of the
bootstrap loader routines. It would then be placed in an application where no programming occurs.
In this case the VPP6 pin should be hardwired to V
DD
.
Warning:
A minimum V
DD
voltage must be applied to the VPP6 pin at all times, including
power-on. Failure to do so could result in permanent damage to the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25
°
C) temperature
only.
E.3.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read
operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0’ which
automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading
the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory
content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,
the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin
must be at the V
DD
level. When entering the STOP mode, the EPROM is automatically set to the
read mode.
Note:
An erased byte reads as $00.
E.3.2
EPROM program operation
Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.
However, the user program can be used to program some EPROM locations if the proper
procedure is followed. In particular, the programming sequence must be running in RAM, as the
TPG