
MOTOROLA
A-4
MC68HC05B6
Rev. 4
MC68HC05B4
14
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
Table A-2
Register outline
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on
reset
Undefined
Undefined
Undefined
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
PC2/
ECLK
PD2/
AN2
Port D data (PORTD)
$0003
PD7/
AN7
PD6/
AN6
PD5/
AN5
PD4/
AN4
PD3/
AN3
PD1/
AN1
PD0/
AN0
Undefined
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
ECLK control
A/D data (ADDATA)
A/D status/control (ADSTAT)
Pulse length modulation A (PLMA)
Pulse length modulation B (PLMB)
Mscellaneous
$0004
$0005
$0006
$0007
$0008
$0009 COCO ADRC ADON
$000A
$000B
$000C POR
(1)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
001 000
0
0
0
0
ECLK
0
0
0
0
CH3
CH2
CH1
CH0
INTP
INTN
INTE
SFA
SFB
SM WDOG
(2)
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
R8
T8
M
WAKE CPOL CPHA LBCL uuuu uuuu
TIE
TCIE
RIE
ILIE
TE
TDRE
TC
RDRF
IDLE
OR
RE
NF
RWU
FE
SBK
0000 0000
1100 000u
0000 0000
ICIE
ICF1
OCIE
OCF1
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
TOF
ICF2
OCF2
uuuu uuuu
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
TPG