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參數(shù)資料
| 型號： | 5962-0720601VXC |
| 元件分類： | ADC |
| 英文描述： | 3-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP52 |
| 封裝： | CERAMIC, QFP-52 |
| 文件頁數(shù)： | 19/21頁 |
| 文件大小： | 433K |
| 代理商： | 5962-0720601VXC |
TIMING CHARACTERISTICS
(1)(Unchanged after 100 kRad)
www.ti.com ....................................................................................................................................................................................................... SLWS194 – MAY 2008
Typical values at TC = 25°C, Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS
PARAMETER
MI
TYP MAX UNIT
N
Aperture Time
tA
Aperture delay
500
ps
tJ
Clock slope independent aperture uncertainty (jitter)
150
fs
kJ
Clock slope dependent jitter factor
50
V
Clock Input
tCLK
Clock period
9.5
ns
tCLKH
Clock pulse width high
4.75
ns
tCLKL
Clock pulse width low
4.75
ns
Clock to DataReady (DRY)
tDR
Clock rising 50% to DRY falling 50%
2.2
3.0
4.7
ns
tDR +
tC_DR
Clock rising 50% to DRY rising 50%
ns
tCLKH
tC_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle
7.0
7.8
9.5
ns
clock
Clock to DATA, OVR(2)
tr
Data VOL to data VOH (rise time)
0.6
ns
tf
Data VOH to data VOL (fall time)
0.6
ns
Cycl
L
Latency
3
es
Valid DATA(3) to clock 50% with 50% duty cycle clock
tsu_c
1.8
3.6
ns
(setup time)
th_c
Clock 50% to invalid DATA(3) (hold time)
2.6
4.1
ns
DataReady (DRY)/DATA, OVR(2)
Valid DATA(3) to DRY 50% with 50% duty cycle clock
tsu(DR)_50%
0.9
1.40
ns
(setup time)
DRY 50% to invalid DATA(3) with 50% duty cycle clock
th(DR)_50%
3.9
6.3
ns
(hold time)
(1)
All values obtained from design and characterization.
(2)
Data is updated with clock rising edge or DRY falling edge.
(3)
See VOH and VOL levels.
Copyright 2008, Texas Instruments Incorporated
7
Product Folder Link(s): ADS5424-SP
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