參數(shù)資料
型號: 4450HG/3-K
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA324
封裝: ROHS COMPLIANT, HSBGA-324
文件頁數(shù): 77/92頁
文件大?。?/td> 780K
代理商: 4450HG/3-K
4450 – Data Sheet, DS-0131-06
Page 79
Hifn Confidential
8.12 MDIO Timing
This device supports a subset of the 802.3-2002 MDIO management interface, also known
as the Management Data Input/Output (MDIO) Interface. This interface allows the 4450 to
monitor and control the PHY device(s) that are connected to the network side ports. If the
host system GMAC will control the system PHY device with its own MDIO connection, then
the 4450 pins are unused. When the 4450 acts as the sole system GMAC these pins are
used as defined in the 802.3 MDIO specification and referenced in Section 6.7. Hifn
includes Station Management (STM) Software as a part of it’s SDK.
The 4450 supports the low speed MDIO operating mode, and this is illustrated in Figure 8-
11. In this mode, the MDC clock signal operates at a frequency of 2.5 MHz.
Figure 8-11. Low-speed MDIO Operation
Table 8-13. MDIO Timing
Symbol
Parameter
Min
Max
Units
Tsu
MDIO Setup prior to MDC High
10
ns
Thold
MDIO Hold after MDC High
10
ns
Tprop
MDC to MDIO Output Delay
0
20
ns
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