參數(shù)資料
型號(hào)： 4450HG/3-K
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA324
封裝： ROHS COMPLIANT, HSBGA-324
文件頁(yè)數(shù)： 38/92頁(yè)
文件大?。?/td> 780K
代理商： 4450HG/3-K
4450 – Data Sheet, DS-0131-06
Page 43
Hifn Confidential
Table 6-8 contains the pin descriptions for the RGMII/RTBI host interface port when
configured in PHY mode.
6.2.3
Network
GMAC RGMII/RTBI Interface Usage
This section discusses the use of GMAC interfaces for the network side interfaces n0 or n1
when configured to support operation in RGMII or RTBI modes.
6.2.3.1
Network GMAC RGMII/RTBI Pin Mappings
Table 6-8. 4450 RGMII/RTBI Host pin descriptions - PHY mode
Pin Name
RGMII/RTBI Signal
I/O
Description
hx_clk_1
hx_txc
in
The receive reference clock will be 125MHz,
25MHz or 2.5MHz.
hx_bus1[4]
RGMII: hx_tx_ctl
RTBI: hx_txd[4]
in
In RTBI mode, contains the fifth bit on the
rising edge of rxc and the tenth bit on the
falling edge of rxc.
In RGMII mode, rxdv on the rising edge of
rxc and a logical derivative of rxdv (i.e., rxdv
XOR rxerr) on the falling edge of rxc.
hx_bus1[3:0]
hx_txd[3:0]
in
In RTBI mode, contains bits [3:0] on the
rising edge of rxc and bits [8:5] on the
falling edge of rxc.
In RGMII mode, bit [3:0] on rising edge of
rxc, bits [7:4] on the falling edge of rxc.
hx_clk_0
hx_rxc
out
The transmit reference clock will be 125MHz,
25MHz or 2.5MHz.
hx_bus0[4]
RGMII: hx_rx_ctl
RTBI: hx_rxd[4]
out
In RTBI mode, contains the fifth bit on the
rising edge of txc and the tenth bit on the
falling edge of rxc.
In RGMII mode, rxdv on the rising edge of
rxc and a logical derivative of rxdv(rxdv XOR
rxerr) on the falling edge of rxc.
hx_bus0[3:0]
hx_rxd[3:0]
out
In RTBI mode, contains bits [3:0] on the
rising edge of txc and bits [8:5] on the
falling edge of txc.
In RGMII mode, bit [3:0] on rising edge of
txc, bits [7:4] on the falling edge of txc.
Note
1. hx = h0 or h1
Table 6-9. 4450 RGMII/RTBI MAC/PHY modes Network pin mappings
Pin Name
MAC-RGMII
MAC-RTBI
PHY-RGMII
PHY-RTBI
RGMII Signal
I/O
RTBI Signal
I/O
RGMII Signal I/O
RTBI Signal
I/O
nx_clk_1
nx_rxc
in
nx_rxc
in
nx_txc
in
nx_txc
in
nx_ctrl_1
nx_rx_ctl
in
nx_rxd[4]
in
nx_tx_ctl
in
nx_txd[4]
in
nx_bus1[3:0]
nx_rxd[3:0]
in
nx_rxd[3:0]
in
nx_txd[3:0]
in
nx_txd[3:0]
in
nx_clk_0
nx_txc
out
nx_txc
out
nx_rxc
out
nx_rxc
out
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