參數(shù)資料
型號： 4450HG/3-K
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA324
封裝： ROHS COMPLIANT, HSBGA-324
文件頁數(shù)： 24/92頁
文件大小： 780K
代理商： 4450HG/3-K
4450 – Data Sheet, DS-0131-06
Page 30
Hifn Confidential
There are two pins that are sampled coming out of Reset and control the boot process,
dpu_gpio[1]/boot_config_1 and dpu_gpio[0]/boot_config_0. These two pins are
further defined in Section 6.7. Table 5-1 summarizes how these two pins are used to
control the boot process.
If the boot_config_1 pin is tied high it indicates that the 4450 has a Flash device
connected. In order to boot from a Flash device, a minimal amount of SDRAM must be
connected to the 4450. If boot_config_1 is tied low it indicates that there is no Flash
device connected to 4450, and the pre-boot code attempts to download boot code from
one of the host Ethernet ports.
The boot_config_0 pin indicates if downloading boot code from one of the host GMAC
ports is permitted. This can be useful for FIPS 140-2 subsystem certification. If the
boot_config_1 pin is pulled low, then booting from one of the host GMAC ports is allowed.
If boot_config_0 pin is pulled high, then booting from the host 0 or host 1 GMAC port is
not allowed.
The eSC processor first looks at the boot_config_1 pin to see if a Flash is present. Then
the DPU will look at boot_config_0 to see if listening to the host GMAC ports is allowed.
If there is no Flash device (boot_config_1 = 0) or the Flash boot fails, and listening to
the host port times out (eSC listening to RMII port and DPU listening to host ports), then
the eSC and DPU will each listen to each other for booting across the inter-connect bus
used for inter-processor communication.
For full details on the software boot load process, refer to the 44x0/84x0 User's Manual.
Table 5-1. Boot Process Summary
dpu_gpio[1]/
boot_config_1
dpu_gpio[0] /
boot_config_0
DPU Boots from:
eSC Boots from:
Comments
00
Host 0/1 GMAC
or eSC inter-
connect bus
RMII port or
DPU inter-
connect bus
Normal system
No Flash
01
eSC inter-
connect bus only
(No GMAC)
RMII port.
FIPS-140 secure system
boot1
No flash
10
Flash Fail to
Host GMAC or
eSC
Flash. Fail to
DPU or RMII
Normal system
With Flash2
11
Flash Fail to eSC
Only (No Host
GMAC boot)
Flash Fail to DPU
or RMII
FIPS-140 secure system
boot1
With Flash2
Note
1. A secure system boot is referring to a design where it is required to carefully control where the
bootload software image comes from (such as in a FIPS-140 design). In such a system, a design may
utilize a secure control processor attached to the RMII port for bootload and device management. These
boot pin settings will not allow a boot image to be delivered over the GMAC host (or network) ports.
Contact Hifn for availability of software support for this feature.
2. The SDRAM must be populated.
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