參數(shù)資料
型號： 4450HG/3-K
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA324
封裝： ROHS COMPLIANT, HSBGA-324
文件頁數(shù)： 50/92頁
文件大?。?/td> 780K
代理商： 4450HG/3-K
4450 – Data Sheet, DS-0131-06
Page 54
Hifn Confidential
External SA storage for the DPU (if additional SAs are required beyond the internal
maximum number)
eSC Code Storage and data memory (i.e., on-chip IKE)
DPU/PCP Code Storage (Optional)
The 4450 provides a 32-bit DDR2 SDRAM interface that supports a single 200/400MHz
SDRAM device and storage capacities from 2 MBytes up to 512 MBytes. A 7 bit ECC
interface is optionally supported on the DDR2 SDRAM Interface.
Table 6-17 indicates the supported memory configurations for the DDR SDRAM.
Table 6-16. DDR2 Interface Signal Definition
Pin Name
SDRAM Signal
I/O
Description
sdclk_diff_n
CK
out
SDRAM Clock
sdclk_diff_p
CK_N
out
SDRAM Clock inverted
sdclk_fb_i
NA
in
DDR2 SDRAM De-skew PLL feedback clock
input
sdclk_fb_o
NA
out
DDR2 SDRAM De-skew PLL feedback clock
output
cs_n
CS_N
out
Chip Select (active low)
ras_n
RAS_N
out
Row address strobe (active low)
cas_n
CAS_N
out
Column address strobe (active low)
we_n
WE_N
out
Write Enable (active low)
ba[2]
BA[2]
out
Bank Address
ba[1:0]
BA[1:0]
out
Bank Address
a[13]/cke
a[13]
out
Address 13/Clock Enable
a[12:0]
A[12:0]
out
Address
dm[3:0]
DM[3:0]
out
Data Mask
dqs[3:0]
DQS[3:0]
in/out
Data Strobe (one per byte)
dq[31:0]
DQ[31:0]
in/out
Data input/output
ecc[6:0]
ECC[6:0]
in/out
ECC data input/output
ecc_dm
ECC_DM
out
ECC data mask
eccs
ECCS
in/out
ECC strobe
odt
ODT
out
DDR2 on-die termination control
相關(guān)PDF資料
PDF描述
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