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參數(shù)資料
| 型號(hào)： | 39VF6401 |
| 廠商： | Silicon Storage Technology, Inc. |
| 元件分類： | FLASH |
| 英文描述： | 64 Mbit (x16) Multi-Purpose Flash Plus |
| 中文描述： | 64兆位（x16）的多功能閃存+ |
| 文件頁數(shù)： | 2/32頁 |
| 文件大小： | 513K |
| 代理商： | 39VF6401 |
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2
Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
2003 Silicon Storage Technology, Inc.
S71223-03-000
11/03
To meet high density, surface mount requirements, the
SST39VF160x/320x/640x are offered in 48-lead TSOP
and 48-ball TFBGA packages. See Figures 1 and 2 for
pin assignments.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39VF160x/320x/640x also have the
Auto Low
Power
mode which puts the device in a near standby
mode after data has been accessed with a valid Read
operation. This reduces the I
DD
active read current from
typically 9 mA to typically 3 μA. The Auto Low Power mode
reduces the typical I
DD
active read current to the range of 2
mA/MHz of Read cycle time. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no
access time penalty. Note that the device does not enter
Auto-Low Power mode after power-up with CE# held
steadily low, until the first address transition or CE# is
driven high.
Read
The Read operation of the SST39VF160x/320x/640x is
controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 3).
Word-Program Operation
The SST39VF160x/320x/640x are programmed on a
word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program
operation is accomplished in three steps. The first step is
the three-byte load sequence for Software Data Protection.
The second step is to load word address and word data.
During the Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is
the internal Program operation which is initiated after the
rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted within 10 μs. See Figures 4 and 5 for WE# and CE#
controlled Program operation timing diagrams and Figure
19 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform addi-
tional tasks. Any commands issued during the internal Pro-
gram operation are ignored. During the command
sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF160x/320x/640x offer both Sec-
tor-Erase and Block-Erase mode. The sector architecture
is based on uniform sector size of 2 KWord. The Block-
Erase mode is based on uniform block size of 32 KWord.
The Sector-Erase operation is initiated by executing a six-
byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte
command sequence with Block-Erase command (50H)
and block address (BA) in the last bus cycle. The sector or
block address is latched on the falling edge of the sixth
WE# pulse, while the command (30H or 50H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms and Figure 23 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
μs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ
2
toggling and DQ
6
at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
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