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參數(shù)資料
| 型號： | 33984 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 mз) |
| 中文描述： | 雙智能大電流的自我保護硅高邊開關(guān)（4.0mз） |
| 文件頁數(shù)： | 21/28頁 |
| 文件大小： | 492K |
| 代理商： | 33984 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
21
MODES OF OPERATION
The 33984 has four operating modes: Sleep, Normal, Fault,
and Fail-Safe.
Table 11
summarizes details contained in
succeeding paragraphs.
Sleep Mode
The default mode of the 33984 is the Sleep mode. This is the
state of the device after first applying battery voltage (V
PWR
),
prior to any I/O transitions. This is also the state of the device
when the WAKE and
RST
are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The device will transition to the Normal or Fail-Safe operating
modes based on the WAKE and
RST
inputs as defined in
Table 11
.
Normal Mode
The 33984 is in Normal mode when:
V
PWR
is within the normal voltage range.
RST
terminal is logic [1].
No fault has occurred.
Fail-Safe Mode
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or
RST
input terminal
transitions from logic [0] to logic [1]. The WAKE input is capable
of being pulled up to V
PWR
with a series of limiting resistance
that limits the internal clamp current according to the
specification.
The watchdog timeout is a multiple of an internal oscillator
and is specified in
Table 7
,
page 18
.
As long as the WD bit (D7)
of an incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the programmed
value of the WDR the device will operate normally. If an internal
watchdog timeout occurs before the WD bit, the device will
revert to a Fail-Safe mode until the device is reinitialized.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI terminal,
regardless of the state of the various direct inputs and modes
(
Table 12
). In this mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, and
OCLT). Then the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in fail-safe mode. The device can be brought out of the
Fail-Safe mode by transitioning the WAKE and
RST
terminals
from logic [1] to logic [0] or forcing the FSI terminal to logic [0].
Table 11
summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
Loss of V
DD
If the external 5.0 V supply is not within specification, or even
disconnected, all register content is reset. The two outputs can
still be driven by the direct inputs IN1:IN0. The 33984 uses the
battery input to power the output MOSFET-related current
sense circuitry and any other internal logic providing fail-safe
device operation with no V
DD
supplied. In this state, the
watchdog, overvoltage, overtemperature, and overcurrent
circuitry are fully operational with default values.
Table 11. Fail-Safe Operation and
Transitions to Other 33984 Modes
Mode
FS
WAKE
RST
WDTO
Comments
Sleep
x
0
0
x
Device is in Sleep mode.
All outputs are OFF.
Normal
1
x
1
No
Normal mode. Watchdog
is active if enabled.
Fault
0
1
x
No
The device is currently in
Fault mode. The faulted
output(s) is (are) OFF.
0
x
1
Fail-
Safe
1
0
1
Yes
Watchdog has timed out
and the device is in Fail-
Safe mode. The outputs
are as configured with the
RFS resistor connected to
FSI.
RST
and WAKE must
be transitioned to logic [0]
simultaneously to bring
the device out of the Fail-
Safe mode or momentarily
tied the FSI terminal to
ground.
1
1
1
1
1
0
x = Don’t care.
Table 12. Output State During Fail-Safe Mode
RFS (k
)
High-Side State
0
Fail-Safe Mode Disabled
6.0
Both HS0 and HS1 OFF
15
HS0 ON, HS1 OFF
30
Both HS0 and HS1 ON
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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|---|---|
| 33984B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-Current Self Protected Silicon High-Side Switch (4.0 mohm) |
| 33984B_09 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mΩ) |
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| 33984C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mΩ) |
| 33-987-BU | 制造商:GC Electronics 功能描述: |
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