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參數(shù)資料
| 型號(hào)： | 33984 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 mз) |
| 中文描述： | 雙智能大電流的自我保護(hù)硅高邊開關(guān)（4.0mз） |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 492K |
| 代理商： | 33984 |
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33984
18
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
A logic [1] on bit D2 disables the overcurrent low (CD dis)
detection timeout feature. A logic [1] on bit D3 disables the open
load (OL) detection feature.
Address x100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state of bit D7. A write to this register when bit D7 is logic [0] will
configure the direct input control for the HS0. Similarly, if D7 is
logic [1] when this register is written, then HS1 is configured.
A logic [0] on bit D1 will enable the output for direct control by
the IN terminal. A logic [1] on bit D1 will disable the output from
direct control. While addressing this register, if the input was
enabled for direct control, a logic [1] for the D0 bit will result in
a Boolean AND of the IN terminal with its corresponding D0
message bit when addressing the OCR register. Similarly, a
logic [0] on the D0 terminal results in a Boolean OR of the IN
terminal with the corresponding message bits when addressing
the OCR register.
The DICR register is useful if there is a need to
independently turn on and off several loads that are PWM’d at
the same frequency and duty cycle with only one PWM signal.
This type of operation can be accomplished by connecting the
pertinent direct IN terminals of several devices to a PWM output
port from the MCU and configuring each of the outputs to be
controlled via their respective direct IN terminal. The DICR is
then used to Boolean AND the direct IN(s) of each of the
outputs with the dedicated SPI bit that also controls the output.
Each configured SPI bit can now be used to enable and disable
the common PWM signal from controlling its assigned output.
A logic [1] on bit D2 is used to select the high ratio (C
SR1
,
1/41000) on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (C
SR0
, 1/20500).
A logic [1] on bit D3 is used to select the high speed slew rate
for the selected output. The default value [0] corresponds to the
low speed slew rate.
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register configures the device with a
programmable time delay that is active during Output ON
transitions initiated via SPI (not via direct input).
A write to this register configures both outputs for different
delay. Whenever the input is commanded to transition from
logic [0] to logic [1], both outputs will be held OFF for the time
delay configured in the OSDR. The programming of the
contents of this register have no effect on device fail-safe mode
operation. The default value of the OSDR register is 000,
equating to no delay. This feature allows the user a way to
minimize inrush currents, or surges, thereby allowing loads to
be switched ON with a single command. There are eight
selectable output switching delay times that range from 0 ms to
525 ms (refer to
Table 6
).
Address 1101—Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1:D0. When D1:D0 bits are programmed for the desired
watchdog timeout period, the WD bit (D7) should be toggled as
well, ensuring the new timeout period is programmed at the
beginning of a new count sequence (refer to
Table 7
).
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows devices
to not be affected by commands being clocked over a daisy-
chained SPI configuration, and by toggling the WD bit (D7), the
watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
Table 5. Overcurrent Low Detection
Blanking Time
OCLT[1:0]
Timing
00
155 ms
01
10 ms
10
1.2 ms
11
150
μ
s
Table 6. Switching Delay
OSD[2:0] (D2:D0)
Turn ON Delay (ms)
HS0
Turn ON Delay (ms)
HS1
000
0
0
001
75
0
010
150
150
011
225
150
100
300
300
101
375
300
110
450
450
111
525
450
Table 7. Watchdog Timeout
WD[1:0] (D1:D0)
Timing (ms)
00
620
01
310
10
2500
11
1250
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 33984B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-Current Self Protected Silicon High-Side Switch (4.0 mohm) |
| 33984B_09 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mΩ) |
| 33984B_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current |
| 33984C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mΩ) |
| 33-987-BU | 制造商:GC Electronics 功能描述: |
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