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參數(shù)資料
| 型號： | 33984 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 mз) |
| 中文描述： | 雙智能大電流的自我保護硅高邊開關(guān)（4.0mз） |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 492K |
| 代理商： | 33984 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
19
Address 1110—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register can be used to disable or enable
overvoltage and/or undervoltage protection. By default
(logic [0]), both protections are active. When disabled, an
undervoltage or overvoltage condition fault will not be reported
in the output fault register.
Address x111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Serial Output Communication (Device Status Return
Data)
When the
CS
terminal is pulled low, the output status register
is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI terminal. The
first eight bits of data clocking out of the SO, and following a
CS
transition, are dependant upon the previously written SPI word.
Any bits clocked out of the SO terminal after the first eight will
be representative of the initial message bits clocked into the SI
terminal since the
CS
terminal first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
A valid message length is determined following a
CS
transition of logic [0] to logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A valid
message length is a multiple of eight bits. At this time, the SO
terminal is tri-stated and the fault status register is now able to
accept new fault status information.
The output status register correctly reflects the status of the
STATR-selected register data at the time that the
CS
is pulled
to a logic [0] during SPI communication and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage V
PWR
condition should be
ignored.
The
RST
terminal transition from a logic [0] to logic [1]
while the WAKE terminal is at logic [0] may result in
incorrect data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following this condition should be ignored.
Serial Output Bit Assignment
The 8 bits of serial output data depend on the previous serial
input message, as explained in the following paragraphs.
Table 8
summarizes the SO register content.
Bit OD7 reflects the state of the watchdog bit (D7) addressed
during the prior communication. The value of the previous D7
will determine which output the status information applies to for
the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO
data will represent information ranging from fault status to
register contents, user selected by writing to the STATR bits
D2:D0. Note that the SO data will continue to reflect the
information for each output (depending on the previous D7
state) that was selected during the most recent STATR write
until changed with an updated STATR write.
Table 8. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
s
0
0
0
s
OTFs
OCHFs
OCLFs
OLFs
UVF
OVF
FAULTs
x
0
0
1
x
0
0
1
CSNS1
EN
IN1_SPI
CSNS0
EN
IN0_SPI
s
0
1
0
s
0
1
0
SOCHs
SOCL2s
SOCL1s
SOCL0s
s
0
1
1
s
0
1
1
OL DIS s
CD DIS s
OCLT1s
OCLT0s
s
1
0
0
s
1
0
0
FAST SR s
CSNS high s
IN DIS s
A/Os
0
1
0
1
0
1
0
1
FSM_HS0
OSD2
OSD1
OSD0
1
1
0
1
1
1
0
1
FSM_HS1
WDTO
WD1
WD0
0
1
1
0
0
1
1
0
IN1 Terminal IN0 Terminal FSI Terminal
WAKE
Terminal
1
1
1
0
1
1
1
0
–
–
UV_dis
OV_dis
x
1
1
1
–
–
–
–
–
–
–
–
s = Selection of output: logic [0] = HS0, logic [1] = HS1.
x = Don’t care.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 33984B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-Current Self Protected Silicon High-Side Switch (4.0 mohm) |
| 33984B_09 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mΩ) |
| 33984B_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current |
| 33984C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mΩ) |
| 33-987-BU | 制造商:GC Electronics 功能描述: |
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