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參數(shù)資料
| 型號： | 29LV400C-90 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY |
| 中文描述： | 4分位[為512k × 8 / 256K × 16] CMOS單電壓3V時(shí)僅閃存 |
| 文件頁數(shù)： | 17/68頁 |
| 文件大小： | 906K |
| 代理商： | 29LV400C-90 |
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17
P/N:PM1155
MX29LV400C T/B
REV. 1.5, APR. 24, 2006
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data# Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.
If Data# Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data# Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
DATA PROTECTION
The MX29LV400C T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down tran-
sition or system noise.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
POWER-UP SEQUENCE
The MX29LV400C T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET# pin to VID(11.5V-12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET# pin, all the previously protected sectors are pro-
tected again.
If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector maynot be re-
used, (other sectors are still functional and can be re-
used).
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
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