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參數(shù)資料
| 型號： | 28F400BV-TB |
| 廠商： | Intel Corp. |
| 英文描述： | 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 4兆位（256 × 16，為512k × 8）SmartVoltage啟動塊閃存系列 |
| 文件頁數(shù)： | 10/49頁 |
| 文件大?。?/td> | 427K |
| 代理商： | 28F400BV-TB |
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SMART 3 ADVANCED BOOT BLOCK
–WORD-WIDE
E
10
PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
19
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19]
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is de-selected or the
outputs are disabled.
DQ
0
–DQ
7
INPUT/OUTPUT
DQ
8
–DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and intelligent identifier data. The data pins float to tri-state
when the chip is de-selected.
CE#
INPUT
CHIP ENABLE:
Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby
current will increase due to current flow through the CE# and RP# inputs.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data
buffers during an array or status register read. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode
, which drives the outputs to High-Z, resets the Write State
Machine, and draws minimum current.
When RP# is at logic high, the device is in standard operation
.
When RP# transitions from logic-low to logic-high, the device defaults to
the read array mode.
WP#
INPUT
WRITE PROTECT:
Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked
,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked
and
can be programmed or erased.
See Section 3.3 for details on write protection.
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| 28F400BX-TB | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 28F410-100M1 | 4M-BIT (512K X 8) CMOS FLASH MEMORY |
| 28F512 | 512K(64Kx8)CMOS FLASH MEMORY |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F400BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBIT (256K X 16. 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BX-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBIT (256K X 16. 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| 28F400BX-TB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BX-TL/BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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